Lattice expands support for open source LatticeMico32 embedded soft microprocessor core

Device support for LatticeMico32 embedded soft microprocessor core now includes the new LatticeXP2 FPGA family, expanded software development support, and peripheral IP.
By Clive Maxfield

Programmable Logic DesignLine
(07/24/2007 1:21 PM EDT)

Lattice Semiconductor has announced expanded support for its LatticeMico32 32-bit embedded RISC microprocessor, an open source, soft IP core optimized for Lattice Field Programmable Gate Arrays (FPGAs).

Availability of this enhanced solution, including new development tool and peripheral IP support, coincides with the release of Lattice's ispLEVER version 7.0 design tool suite. Core optimization for the new non-volatile LatticeXP2 FPGA family, the industry's first "true" 90 nm FPGA using on-chip Flash technology, is also now available.

"System designers are enthusiastically embracing our open source LattticeMico32 microprocessor platform solution," said Stan Kopec, corporate vice president of marketing. "The processor and peripheral capabilities of the LatticeMico32 system, combined with the unique silicon features in our non-volatile LatticeXP2 FPGA family, provide a simpler and more efficient way for system designers to create products that must retain configuration and dynamic state information between power-up cycles."

The LatticeMico32 soft core on the LatticeXP2 FPGA
The LatticeXP2 FPGA combines Flash and SRAM technology on a single 90 nm die, enabling unique capabilities such as "instant-on" operation, encrypted design security and flashBAK block RAM back-up. The LatticeMico32 processor, in combination with the LatticeXP2 devices, provides these benefits to designers:

• Instant Code Execution - By taking advantage of the high-speed configuration of the LatticeXP2 devices (~1 ms), the microprocessor can begin code execution almost immediately upon device power-up.
• flashBAK – The previous operating context, both logic configuration as well as RAM contents, is available to the microprocessor at power-up through use of the unique flashBAK feature found in the LatticeXP2 devices. This feature allows the microprocessor to store important information, such as error codes or performance conditions, into non-volatile memory before power down. At power-up the information is automatically reloaded into the microprocessor memory to resume operation.
• Security – Security of design code (both microprocessor software and FPGA hardware) is inherently high because configuration data is stored in on-chip Flash. In addition, LatticeXP2 devices offer other security and protection features, such as 128-bit AES encrypted design bitstream support and a keyed "Lock" feature that protects against accidental or unauthorized device programming.

Enhanced software development tool flow
Lattice's ispLEVER design tool suite version 7.0 has expanded support for software coding and debug with the addition of new tools to the Integrated Development Environment (IDE):

• Code Trace – a tool that allows a programmer to trace the execution of program source code for debug.
• Standard Make C and C++ Projects – provide support for programmers to create Standard Make projects, in addition to the existing Managed Make, wizard-driven project creation process.
• Small C library – based on the Newlib C library source, Small C focuses on efficient compilation for embedded applications.

Additional peripheral IP cores
Several new and updated peripheral IP cores are available with the release of ispLEVER 7.0 for use with the LatticeMico32 processor. These user configurable designs include:

• DDR2 SDRAM Controller – Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) Controller.
• Tri-Speed MAC – Ethernet Media Access Controller operates in Gigabit or Fast Ethernet (10/100 Mbps) modes.
• Single Data Rate (SDR) SDRAM Controller – now available on the LatticeXP2 devices for use with the LatticeMico32 processor.
• SPI Flash ROM – the Serial Peripheral Interface (SPI) Flash memory controller provides an invisible interface between a LatticeMico32 microprocessor and an external, industry-standard SPI Flash chip.

These peripherals join a number of LatticeMico32 peripheral functions previously introduced, including Timer, UART, GPIO, DMA controller and other blocks.

Pricing and availability
The LatticeMico32 System development tools are available now for the LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, LatticeECP2, LatticeECP2M, LatticeECP, and LatticeEC FPGA families. The tools can be downloaded at no charge from the LatticeMico32 Center (Click Here for more details).

Lattice's Standard LatticeXP2 development board can be used for LatticeMico32 development and is priced at $695. The ispLEVER design tool kit for Windows is priced at $895.

Emailing: [VHDL] 03 - 클럭 위상차 만들기

 

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[VHDL] 03 - 클럭 위상차 만들기

하드웨어

2005/12/30 15:26

http://blog.naver.com/too_unique/100020646392

로직을 구성하다 보면, 속도 문제나 타이밍 문제가 발생할 경우 클럭의 속도를 조정해야 할 필요가있다. 시스템 클럭을 VCO(Voltage Control Oscilator)에서 4분주하면, 클럭의 속도 조정을 반클럭 단위가 아니라 1/4클럭 단위로 조정 할 수 있어서 속도 향상이나 타이밍 조정을 좀더 쉽게 할 수 있다.

 

-- Clk_Gen.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Entity Clk_gen is
    Port(
  clk_in : in std_logic;    --클럭입력
  div2_r : out std_logic;   --2분주 라이징 에지
  div2_f : out std_logic;   --2분주 폴링 에지
  div4_r : out std_logic;   --4분주 라이징 에지
  div4_f : out std_logic;   --4분주 폴링 에지
          );
End Clk_gen;

Architecture arch_Clk_gen of Clk_gen is
 signal div2_re : std_logic := '0';
 signal div2_fe : std_logic := '0';
 signal div4_re : std_logic := '0';
 signal div4_fe : std_logic := '0';
Begin
 div2_r <= div2_re;
 div2_f <= div2_fe;
 div4_r <= div4_re;
 div4_f <= div4_fe;

Clock_div : Process(clk_in)
 Begin
  If clk_in'event and clk_in = '1' then
   div2_re <= not div2_re;
   --rizing-falling edge가 바뀐것은 클럭 이벤트와 동시에 판단하고, 이전값이 기준이므로
   If div2_re = '1' then
    div4_fe <= not div4_fe;
   Else
    div4_re <= not div4_re;
   End If;
  Elsif clk_in'event and clk_in = '0' then
   div2_fe <= div2_re; --폴링에지는 항상 라이징에지 뒤에 오게 하기위해서 라이징에지값 이용
        End If;
    End process;
 End Process;
End arch_Clk_gen;

Emailing: [VHDL] 02-홀수클럭 분기

 

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[VHDL] 02-홀수클럭 분기

하드웨어

2005/12/28 11:50

http://blog.naver.com/too_unique/100020599423

홀수 클럭 분주는 짝수 클럭의 분주와는 조금 다른 프로세스를 거치게 됩니다.

짝수 클럭분주에서는 원하는 클럭의 절반까지만 카운트 하면 되지만, 홀수에서는 원하는 클럭 만큼 카운트 해야 문제 없이 분주가 이루어 지기 때문에 사용되는 어레이가 좀더 늘어나게 됩니다.(물론 다른 방법을 사용해서 줄여주는 방법도 있지만 기본적인 정석으로 설명할까 합니다.)

또한 홀수분주의 클럭 카운터에서는 라이징 에지와 폴링 에지를 모두 이용해야 하므로, 두개의 프로세스로 나누어서 구성해야 합니다.

VHDL에서는 하나의 프로세스에서 동일한 신호가 라이징 에지와 폴링에지를 모두 이용할 수 없기 때문에 별도의 신호를 만들어서 동작하도록 해야 하기 때문입니다.

 

아래는 5분주를 하는 클럭의 코드 입니다.

-- Clk_Gen.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Entity Clk_gen is
    Port(
  clk_in : in std_logic;    --클럭입력
  div5 : out std_logic    --5분주 클럭
          );
End Clk_gen;

Architecture arch_Clk_gen of Clk_gen is
 signal cnt_div : std_logic_vector(2 downto 0) := "111";
 signal div_temp : std_logic := '0';
Begin
counter : Process(clk_in)
 Begin
  If clk_in'event and clk_in = '1' then
   cnt_div <= cnt_div + '1';
   If cnt_div = 4 then
    cnt_div <= "000";
   End If;
 End If;
    End process;
div5_clock : Process(clk_in, cnt_div)
 Begin
  If (cnt_div > 2 or (cnt_div = 2 and clk_in = '0')) then
   div5 <= '0';
  Else
   div5 <= '1';
  End If;
 End Process;
End arch_Clk_gen;

 

확실히 검증까지는 안해봐서 에러 없이 동작 하는지는 확인을 안해봤네요 하지만 문제는 없을 것이구요.

 

대신 다른 문제점이 숨어 있습니다.(공부하는 초반에는 걱정할 필요가 없긴 합니다만, 실제 구성에서는 매우 치명적인 문제가 될 소지가 있지요)

문제는 역시 폴링 에지를 이용하는 클럭 반전 위치 에서인데요.

이부분을 처리하는 과정에서 위의 코드를 그대로 쓴다면, 프로그램이나, 실제 사용할 FPGA, CPLD등의 게이트 성능에 따라서 게이트 시간 차에 의한 클리핑이 발생할 수 있습니다.

이 결과를 확인하는 방법은 역시 시뮬레이션인데 폴링에지에서 반전되는 클럭을 확대해서 보시면 나올 수도 있습니다.

Emailing: [VHDL]01-클럭 짝수분주

 

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[VHDL]01-클럭 짝수분주

하드웨어

2005/12/26 10:55

http://blog.naver.com/too_unique/100020557554

VHDL을 하면서 가장 처음 접하는것이 클럭 분주일 것입니다.

가장 간단하면서도 가장 많이 쓰이고, 가장 중요한 것이기 때문이지요.

 

짝수분주는 단순히 자신이 원하는 분주의 수를 반으로 나눠서 그 위상을 반전시켜주기만 하면 아주 간단 합니다.

물론 분주의 숫자가 커지면 카운터를 사용하는것이 간단하게 구성되지만, 2분주나 4분주 같은경우에는 굳이 카운터를 쓰지 않아도 되지요..

 

2분주를 하기 위해서 필요한건 사실 FF하나만 쓰면 되니까 정말 필요한건 거의 없구요.

우선 2분주의 예를 보겠습니다.

 

-- Clk_div2.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity Clk_div2 is
    Port(
  clk_in : in std_logic;    --원 소스클럭 입력

  reset : in std_logic;     --초기화를 위한 리셋입력
  div2 : out std_logic      --2분주된 클럭 출력

          );
End Clk_div2;

 

Architecture arch_Clk_div2 of Clk_div2 is
Begin
Clock_div : Process(clk_in)
 Begin

  If reset = '1' then

    div2 <= '0';

  ElsIf clk_in'event and clk_in = '1' then
    div2 <= not div2;
  End If;
 End process;
End arch_Clk_div2;

 

아키텍쳐 부분에서 해주는것 없이 아주 간단하게 해결되지요??

그저 클럭이 high로 바뀔때마다 출력되는 div2의 값을 반전만 시켜주면 2분주가됩니다.

4분주의 경우에는 ElsIf 안에 한번 더 div2가 바뀔때마다 반전 시켜서 출력해 주면 끝이구요..

그 이상의 경우에도 마찬가지 방법을 적용하면 됩니다. 하지만 숫자가 늘어나면 자신도 햇갈리니까 카운터를 쓸 수 밖에 없겠지요??

그럼 이제 카운터를 사용한 16분주를 구성해 보겠습니다.

16분주로 구성하려면 카운터는 8까지 셀 수 있어야 하니까 3비트 카운터가 있어야 되겠군요.

-- Clk_div16.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity Clk_div16 is
    Port(
  clk_in : in std_logic;    --원 소스클럭 입력

  reset : in std_logic;     --초기화를 위한 리셋입력
  div16 : out std_logic    --16분주된 클럭 출력

          );
End Clk_div16;

 

Architecture arch_Clk_div16 of Clk_div16 is

  signal cnt8 : std_logic_vector(2 downto 0); --8개를 세기 위한 3비트 카운터
Begin
Clock_div : Process(clk_in)
 Begin

  If reset = '1' then

    div16 <= '0';

    cnt8 <= "111";                                      --카운터 값을 초기화(리셋이 풀리면 카운터 값이 0이 되고, 이 첫클럭에서 분주를 시작하도록 하기위해서 111을 초기값으로 했습니다.)

  ElsIf clk_in'event and clk_in = '1' then

    cnt8 <= cnt8 + '1';
    If cnt8 = "000" then

      div16 <= not div16;

    End If;
  End If;
 End process;
End arch_Clk_div16;

이것도 역시 엄청 간단하지요??

짝수분주는 위의 예문처럼 아주 간단하게 해결됩니다...

음.. 하지만 위의 카운터를 사용한 16분주에는 정확히 자신이 원하는 결과는 나오지 않을 겁니다.

힌트를 드리자면, 리셋이 풀리면서 첫클럭이 들어올 때 동작한다는 내용이지요.

그래도 클럭은 정확히 16분주가 되지만 첫번째 클럭부터 동작하지는 않는다는 것이지요(사용하는 프로그램에 따라서 000에 반전되는것과, 001에 반전되는것이 있을껍니다.)

이에 관한 내용은 우선 이유를 생각해 보시길... 물론 여기에 관한 내용도 다른 주제로 여기에 올릴 예정 입니다.

2007 제12회 '바다의 날' 기념 마라톤 대회

지난 6월2일, 3월 31일 2007 전마협 하남 하프마라톤대회 이후 두번째로 도전하는 10Km 마라톤... 역시나 힘들어 죽을뻔 했슴...^^;

YouTube - Canon - Trace Bundy

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10 Years Old South Korean Boy Copy 'Canon' in one week.

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http://www.elevenengineering.com/

Wireless Solutions & Semiconductor Technology

Eleven Engineering is a fabless semiconductor company specializing in wireless baseband processors and digital wireless audio modules. Leveraging the multithreaded technology of its XInC™ family of wireless processors, Eleve n has become a global leader in digital wireless audio. The Squeak product line of wireless digital audio modules ship in the WHAM2 form factor which is small and highly integrated to provide designers, developers, and manufactures with drop-in solutions for a wide range of wireless audio applications. All Squeak products employ Eleven's unique adaptive frequency hopping algorithm; WFD (Walking Frequency Diversity) to deliver superior audio quality of service (QoS), even in the crowded 2.4 GHz band. Eleven also offers evaluation kits, development kits, reference designs, and engineering services to facilitate easy integration and reduce time to market.

Silicon
XInC - wireless processor
XInC2 - wireless processor with built-in audio features

Digital Wireless Audio
Squeak 1.5 - high performance digital wireless audio
Squeak 1C - low-power digital wireless audio

Partner Information
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Emailing: Enhanced FPGA suits compute-intensive apps

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Enhanced FPGA suits compute-intensive apps Posted: 01 Nov 2006 Capitalizing on expiring FPGA patents and an accelerating shift of FPGAs into data-path processing, startup Velogix Inc. is developing a high-performance programmable-logic platform to run the billions of operations each second needed by applications like video and imaging, test and measurement, and communications. The platform is planned for unveiling by year's end. As FPGAs grow denser and faster, they cannot only serve as logic-aggregation solutions, but can also take on data-path-dominated designs that demand significant computational capabilities. Such on-chip resources as large amounts of memory and dedicated multiplier-accumulator elements allow these FPGAs to deliver billions of multiply-accumulate operations per second and implement complex system functions. This application shift has been noted by major FPGA suppliers like Xilinx Inc. and Altera Corp., with their latest Virtex and Stratix platforms, respectively, as well as new companies like California-based Velogix. By leveraging the latest processes, FPGAs hit density and performance levels that let the chips do more data-path and computational processing, said Danny Biran, VP of product and corporate marketing at Altera. Whether used as standalone processors or coprocessors, FPGAs can often replace such dedicated functions as DSPs, or can accelerate complex algorithms that the DSP block could not execute fast enough. Altera's electronic system-level design tools make it easier to port algorithms to the FPGA by working at higher levels of abstraction, Birin said. Application-optimized platforms help Xilinx deliver better performance in different market segments, the company's senior manager for DSP marketing, Narinder Lall, said. By offering a different mix of on-chip intellectual property (IP), he said—specifically citing memory, DSP and Serdes—"we can deliver platforms better able to serve the computer, networking and signal-processing markets." Adding more system-level capabilities lets FPGAs deliver performance exceeding that of CPUs. "We are also working with software providers such as Matlab and Simulink to develop tools that make it easier for algorithm developers to port their algorithms without knowing much about the underlying FPGA fabric," said Lall. At Semico Research, Rich Wawrzyniak, senior analyst for ASICs, sees the shift to 65nm as an opportunity for FPGA vendors to increase on-chip resources and provide faster I/O pins. At the high end of the FPGA families, he expects this to give companies a big leap in compute capabilities. These observations confirm research done by Velogix, which expects to deliver a high-performance, high-capacity programmable-logic platform before the year is out. The programmable-logic products now getting final touches will take on system designs in areas like imaging, test and measurement, computation, communications and A/V, said Velogix CEO Vivek Pendharkar. While these markets have existing programmable-logic solutions, Pendharkar said, a breakthrough opportunity exists for new products to handle computationally intensive applications. With ASIC costs escalating, Pendharkar said, the timing is opportune to enter the market. Moreover, since some key programmable-logic patents have expired, there is no longer any patent overlap with the technology in development at Velogix. New platforms will have higher levels of hard IP and a novel fabric core, Pendharkar said. Along with the new fabric, Velogix will also develop easy-to-use system-implementation tools, Pendharkar said, that will deliver shorter compilation times than the tools used for current-generation FPGAs. The first implementations will use Taiwan Semiconductor Manufacturing Co.'s 90nm process technology, he said, and will offer compelling prices and performance. Acceleration's cost is falling as FPGAs offer higher capacities, said Martin Mason, director of silicon product marketing at Actel Corp. General-purpose CPUs and DSPs don't always offer needed flexibility, often making FPGAs the only alternative. SRAM-based FPGAs need dedicated compute blocks to achieve high multiply-accumulate throughputs, but on the fine-grained ProASIC flash-based FPGAs, high-performance multipliers and other compute elements can be implemented in the fabric, Mason said. - Dave Bursky EE Times This article was printed from EE Times-Asia located at: http://www.eetasia.com/ART_8800439900_0_NT_481013b7.HTM Back to Article Home