March 07, 2008
SiliconBlue 65-nm FPGAs run on microamps
SiliconBlue's low-power 65 nm FPGAs come in small ball grid array packages and are intended for use in mobile phones and other handheld devices.
By Peter Clarke
LONDON - SiliconBlue Technologies Corp. (Sunnyvale Calif.) is offering a family of low-power FPGAs implemented on a 65-nm CMOS manufacturing process. The FPGAs, which carry their own non-volatile memory on-chip for holding configuration data, come in small ball grid array packages and are intended for use in mobile phones and other handheld devices.
The company was founded by Kapil Shankar, CEO, a 20-year veteran of the programmable logic industry, and Antti Kokkinen, a partner and cofounder of venture capital firm BlueRun Ventures (Menlo Park, Calif.).
The iCE65 family comprises four members starting with the iCE65L02 with 1,792 logic cells, up to 128 I/O pins and a current consumption of 5mA at 32-MHz clock frequency. At 32-kHz the devices consumes 25-microamps.
At the top of the range is the iCE65L16 with 15,260 logic cells and up to 384 I/O pins. At 32-MHz the device consumes 40-mA but with the clock run down to 32-kHz the device consumes 250-microamps. The product brochure, downloadable from www.siliconbluetech.com does not indicate a maximum clock frequency or current draw at a higher frequency.
By way of a comparison, an Altera MAX IIZ family device fully loaded with 16-bit counters and clocked at 50-MHz has a dynamic power consumption of 8.9-mA and the static power consumption is 29-microamps.
The iCE65 is described as the first non-volatile FPGA to have been implemented on a 65LP CMOS process. Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) is believed to be the foundry making the chips for SiliconBlue. The architecture is said to be scalable to 40-nm and the family is being offered in both volatile and non-volatile memory versions as well as in bare die form for system-in-package integration.
SiliconBlue provides iCEcube design tools to take developers through to the bitstream. It has a graphical user interface and allows timing-driven routing. The iCEman development board comes bundled with the iCEcube software and is based on the iCE65L04 device with 3.520 logic cells, 256 I/O pins, and current consumption of 20-mA at 32-MHz.
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