액텔, 하드형 ARM 코어 통합한 플래시 기반 FPGA 선보여

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액텔, 하드형 ARM 코어 통합한 플래시 기반 FPGA 선보여

게재:2010년05월14일

Dylan McGrath
EE Times

Actel사가 임베디드 디자이너들의 폭 넓은 관심을 끌만한 중요한 발전이라고 밝힌 플래시 기반 FPGA(field programmable gate array) 제품군을 출시했다. 이 FPGA 패브릭은 하드형(hard) ARM Cortex-M3 프로세서로 구축된 완벽한 마이크로컨트롤러 서브시스템 및 프로그램 가능형 아날로그 블록과 통합되어 있다. SmartFusion 제품군의 첫번째 제품은 대량 생산 중으로 현재 이용 가능하다.

Actel사에 따르면, 디자이너들은 SmartFusion 디바이스를 통해 보드 레벨을 변경하지 않고도 하드웨어/소프트웨어 트레이드오프를 즉시 최적화시킬 수 있다고 한다. 프로세서와 필수 글루 로직을 한 디바이스에 제공함으로써 성능과 비용 및 풋프린트의 이점을 제공한다고 Actel사의 경영진들은 밝혔다.

“SmartFusion은 CPU 코어만이 아니라 완전한 마이크로컨트롤러 서브시스템을 갖추고 있다”고 Actel사의 세일즈 및 마케팅 VP인 Rich Kapusta 씨는 말했다. “최초로 성능에 대한 타협 없이 FPGA 및 마이크로컨트롤러를 일부 프로그램 가능형 아날로그와 통합했다.”

컨설팅 업체인 Silicon Insider사의 사장인 Jim Turley 씨에 따르면, 디자이너들은 약 10년 동안 프로세서들을 FPGA에 통합시키기 위해 노력해 왔지만 프로그램 가능형 패브릭과 프로세서 아키텍처가 조화되지 못하고 이 구성요소들 간의 통신이 느려짐으로써 그다지 큰 성공을 이루지 못했다고 한다. “Actel사는 SmartFusion을 통해 일반적인 ARM 프로세서와 FPGA 패브릭을 결합시켰을 뿐만 아니라 이 둘을 원활하게 통신할 수 있는 방식으로 통합시켰다”고 Turley 씨는 말했다.

SmartFusion은 2005년에 시장을 강타한 Actel사의 첫번째 혼성신호 FPGA인 Fusion에서 발전된 제품이다. Fusion 디바이스는 32비트 ARM Cortex-M1 등의 소프트 프로세서 코어를 통합할 수 있다.

Actel사의 마케팅 및 엔지니어링 수석 VP인 Fares Mubarak 씨는 Fusion이 시장에서 성공을 거두긴 했지만 Actel사는 타깃 어플리케이션의 폭을 보다 넓히고 싶어했다고 밝혔다. 이를 위해 Actel사는 프로세서를 강화하고 표준 주변기기에 대한 전체적인 보완 요소를 제공함으로써 프로세서 이외의 성능도 높여야만 했다.

“Actel사는 플래시 공정에 상당한 투자를 했기 때문에 이 새로운 제품군이 누구도 쉽게 복제할 수 없는 지속 가능하며 차별화된 디바이스라는 점에 대해 상당히 만족해 했다”고 Kapusta 씨는 말했다.

SmartFusion은 내장 플래시 메모리를 갖춘 CortexM3를 제공하는 한편, SRAM 기반 FPGA는 외장 플래시를 필요로 한다고 Kapusta 씨는 덧붙였다. 또한 그는 이러한 플래시 기술을 통해 SmartFusion에서 고전압 아날로그가 디지털 회로와 공존할 수 있는 것이라고 설명했다.

Actel사는 SmartFusion이 FPGA, 프로그램 가능형 아날로그 및 마이크로컨트롤러가 교차하는 광범위한 시장의 흥미를 끌 수 있을 것으로 생각하고 있다. SmartFusion은 산업, 군사, 의료, 통신, 컴퓨팅 및 스토리지 시장의 시스템 및 전력 관리, 모터 제어, 산업 자동화, 디스플레이와 같은 다양한 어플리케이션들을 타깃으로 하고 있다.

그러나 Actel사의 경영진들은 SmartFusion이 학습 곡선이 필요할 수도 있다면서, 특히 FPGA는 익숙하지만 마이크로컨트롤러에 대해서는 생소하다거나 그 반대의 상황인 디자이너들의 경우 그러할 것이라고 인정했다.

따라서 Actel사는 이 디바이스를 위한 설계 지원을 위해 Libero IDE(Integrated Design Environment)를 제공하며 GNU를 갖춘 무료 SoftConsole Eclipse 기반 IDE뿐만 아니라 Keil 및 IAR Systems사의 평가 소프트웨어 버전을 제공한다.

Actel사에 따르면, SmartFusion 디바이스에 통합된 마이크로컨트롤러 서브시스템은 ARM Cortex-M3 기반으로 100MHz 동작 속도를 가진다고 한다. 또한 최대 512킬로바이트의 플래시 메모리와 64킬로바이트의 SRAM 등이 포함되어 있다.

SmartFusion 디바이스는 Actel사의 플래시 기반 ProASIC3 FPGA 아키텍처로 제작되고 130나노 CMOS 공정에서 구현되며 6만~50만 개의 시스템 게이트와 350MHz의 성능으로 최대 204개의 입출력을 지원한다.

Actel사는 지난해 9월 이후부터 SmartFusion 디바이스를 샘플링해 왔으며 수십 곳의 고객사들과 협력을 진행해 왔다고 밝혔다. SmartFusion 제품군의 첫번째 제품인 A2F200은 대량 생산 중으로 현재 이용 가능하다. 또한 A2F500 디바이스들은 올해 2분기에 공급될 예정이며 A2F060 디바이스들은 올해 하반기에 공급될 전망이다.

고객 평가를 위한 샘플 개발 킷은 99달러에 제공되고 모든 기능을 갖춘 개발 킷은 999달러에 공급되며 두 개발 킷 모두 현재 바로 사용할 수 있다고 Actel사는 밝혔다.

본 기사는 http://www.eetkorea.com/ART_8800606711_480103_NP_dc456e9e.HTM에 있는 전자 엔지니어 기사에서 인쇄한 것입니다.

Xilinx revisits the embedded-CPU FPGA

Wednesday, April 28, 2010

Nearly a decade ago Xilinx and Altera set a new direction for the FPGA industry, each announcing a high-end FPGA sitting beside a powerful CPUs on one die. Enticed by what had been explosive growth in a networking industry that was in fact using MPUs and high-end FPGAs side by side on their boards, the programmable-logic leaders poured development and marketing dollars into their new flagship ICs, Altera Excalibur and Xilinx Virtex-II Pro.

If this story doesn't sound familiar, it's because the two chips were both doomed to vanish. Within about a year both chips were no longer actively marketed, though you could still buy them. Quiet settled over the scene of the revolution, dust gathered on the engineering notebooks, and both companies silently pledged not to try that again.

Exactly what went wrong is a difficult question. There is always enough blame to go around when an entire product category fails. Certainly the issue was not silicon execution: both the chips were heavily used in the academic community, as the platforms for research that became much of the foundation of today's heterogeneous multicore embedded computing.

Rather, the issues were more practical. By the time they were shipping, Excalibur and Virtex-II Pro were comparatively expensive ways to buy what had become a mature microprocessor. So the significant added cost of the FPGA-based parts was hard to justify for production. There was also the problem of configuration. As any product manager can attest, anything you integrate into a chip is the wrong choice for the next customer you talk to. You have the wrong CPU, or the wrong memory architecture, or not the right peripherals, or not enough or too much FPGA fabric. Finally, and perhaps the most serious problem for both chips, the interface between the CPU and FPGA sides of the die is always problematic. An interface powerful and flexible enough for experienced SoC architects is incomprehensible to traditional FPGA users.

All this notwithstanding, yesterday ARM and Xilinx announced another cut at the challenge: the Extensible Programming Platform (or EPP, if you will allow.) With perhaps a nervous glance over the shoulder to check for the spectre of Virtex-II Pro, the company is positioning this product not as an FPGA with an on-chip CPU, but as a software execution platform that happens to facilitate configurable hardware accelerators and peripherals. The difference may sound like words, but it is more than marketing-program deep.

The EPP is architected somewhat differently from the earlier chips. Like them, it is divided into a processor portion and an FPGA portion. But the EPP's processor side is nearly self-contained, comprising a pair of ARM Cortex-A9MP CPU cores, along with the NEON media engine, the debug core, the recently-released AXI-4 interconnect IP, caches, DRAM controller, and typical peripherals. Xilinx senior vice president of marketing Vincent Ratford pointed out that the CPU side of the chip is sufficiently autonomous that it can boot Linux before the programmable fabric is even configured. The FPGA side will apparently look a lot like a moderate-sized Virtex-6, with fabric, block RAM, probably DSP blocks, and, in some versions, fast SerDes.

The interconnect between the two sides is a more interesting subject. Ratford said that about 2500 signals will cross the boundary between the CPU and FPGA regions. That apparently includes both the high-bandwidth main bus and the peripheral bus of the AXI network. It is not clear just how the multi-layer nature of AXI will be propagated into the FPGA fabric. ARM's multicore coherency bus also will extend into the fabric, according to ARM Physical IP Division executive vice president and general manager Simon Segars. So it should be possible for sophisticated users to implement coherent caches and local memories for accelerators in the FPGA Block RAM.

The chip will use TSMC's 28HPL process, and Xilinx plans to sample at least one version sometime in 2011—a pretty big window. Ratford said there would be several versions of the die with different processor subsystems.

The user design flow will be quite different from the traditional FPGA flow. Ratford said "This product targets the software developers." The concept is that developers—presumably starting with a reference design—would use ARM's RealView Development System to bring up an application in C/C++. Then they would profile the code execution, identify hot spots and critical sequences, and call in the hardware team with behavioral synthesis tools to massage the underperforming C into RTL. From there, the RTL would go into Xilinx's ISE 12 tool chain, eventually becoming a configuration file for the FPGA side of the chip. There are plans to link RVDS and ISE at some critical points to allow debug in both environments at once. Xilinx is also exploring Matlab and Labview as design-origination tools.

So are there enough fundamental differences to predict a better fate for the EPP than overtook the Virtex-II Pro? Some things are indeed profoundly different this time. First, you can put vastly more hardware into a large 28nm die than you could into a big chip ten years ago. That means more performance, a please-almost-everyone selection of peripherals at a decent cost point, room for more capable accelerators, and—desperately important—much more on-chip memory. Second, the ARM architecture is far more ubiquitous today than the PowerPC was then. So even if the big networking vendors are once again unimpressed, many other applications are still available. These two facts should substantially reduce barriers to market acceptance of the new architecture.

Third, EPP will probably be one of the first implementations of Cortex-A9 in 28nm to be available to the general market, not a late-coming and expensive alternative to a two-chip approach. Even though the A9 has been announced for about a year now, many users may find the EPP a very accessible way to get at one. If users see value in the FPGA portion of the die as well, the EPP could look like a good deal. And finally, the EPP is addressed to a very different market than Virtex-II Pro. The earlier chip was aimed at FPGA experts. EPP is addressed to software-dominated design teams in which hardware engineers play a supporting role.

Will it work? There remain two major questions. First, can the kind of software-first methodology Xilinx envisions successfully produce a working SoC with today's tools, or will the design require early engagement by FPGA experts, careful system modeling and parallel hardware and software development? If the latter is the case, much of the advantage of the EPP is lost. Second, can Xilinx hide from designers the complexity of the interface between the CPU and FPGA sides of the die, without obscuring the power of the architecture? Neither software developers nor traditional FPGA users are going to cope successfully with the interface in all its riches. Yet the advantage of the EPP over a commodity microprocessor used with an inexpensive FPGA rests in users' ability to exploit that interface. Only time can answer these two questions.

© Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.

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추천: http://www.edn.com/blog/1690000169/post/110054211.html?rid=#EDNRegVisitorID#&nid=2435

Xilinx Unveils ARM-Based Processing Architecture for Delivering Unrivaled Levels of Performance in Embedded Systems

press release

April 27, 2010, 5:00 p.m. EDT

Xilinx takes processor-centric approach to deliver platform that combines the best of serial and parallel processing

SAN JOSE, Calif., April 27, 2010 /PRNewswire via COMTEX/ -- Embedded Systems Conference -- Xilinx Inc. /quotes/comstock/15*!xlnx/quotes/nls/xlnx (XLNX 26.54, +0.24, +0.91%) today introduced the architecture for a new Extensible Processing Platform that will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM(R) Cortex(TM)-A9 MPCore(TM) processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenging system requirements presented by the global demand for embedded systems to perform increasingly complex functions.

The Xilinx(R) Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing -- or any combination thereof -- needed to meet their application-specific requirements, including lower cost and power.

"Today's embedded software developer is being tasked to build complex applications that require tremendous levels of system performance, and they need to deliver that performance within tightly managed cost, schedule and power budgets," said Vin Ratford, Xilinx Senior Vice President for Worldwide Marketing and Business Development. "By creating an architecture within a familiar ARM processor-based development framework, this new Extensible Processing Platform can be the engine of innovation for many design teams held back today by performance bottlenecks."

A software-centric development flow is enabled by a processor-centric approach which presents a full processor system - including caches, memory controllers and commonly used connectivity and I/O peripherals - that boots and can run a variety of operating systems (OS) at power-up, such as Linux, Wind River's VxWorks and Micrium's uC-OSII. The ARM architecture and its Connected Community ecosystem further maximize productivity for developers of embedded systems, while unrivaled performance is achieved by Xilinx's architecting the subsystem around ARM's dual-core Cortex(TM)-A9 MPCore(TM) processors, each running at up to 800 MHz, combined with the parallel-processing capabilities of Xilinx's high-performance, low-power 28-nanometer programmable logic. The programmable logic is tightly coupled with the processor system through the high-bandwidth AMBA(R)-AXI(TM) interconnects to accelerate key system functions by up to 100x, using off-the-shelf and/or custom IP. This architectural approach addresses common performance bottlenecks between these parallel and serial computing environments, memory and I/O. It also gives the processor system configuration control of the programmable logic, including dynamic reconfiguration.

"Taking advantage of the parallelism of programmable logic is an excellent method for overcoming cost and power challenges in systems that require significant levels of high performance," said Simon Segars, President ARM Inc. "Xilinx's new architecture abstracts much of the hardware burden away from the embedded software developers' point of view, giving them an unprecedented level of control in the development process."

Software developers can leverage their existing system code based on ARM technology and utilize vast off-the-shelf open-source and commercially available software component libraries. Because the system boots an OS at reset, software development can get under way quickly within familiar development and debug environments using tools such as ARM's RealView development suite and related third-party tools, Eclipse-based IDEs, GNU, the Xilinx Software Development Kit and others.

Unrivaled Performance to Enable New Applications

Demand for higher levels of embedded system performance is being driven by end market applications that require multifunctionality and real-time responsiveness, such as automotive driver assistance, intelligent video surveillance, industrial automation, aerospace and defense, and next-generation wireless. In the automotive sector alone, with greater than 50 million cars produced each year, and an estimated 600 million motor vehicles on the road, today's $1.3-billion-dollar driver assistance market is expected to grow to $5.8 billion by in 2017(1) as manufacturers deploy more embedded systems in their vehicles to make them safer.

With statistics showing that 60 percent of front-end collisions could have been avoided with an extra .5-second response time, or that driver fatigue accounts for an estimated 30 percent of all driver fatalities, the motivation to leverage technology to save lives is clear. As developers of driver assistance systems pack more compute power into their applications, radar and infrared sensors, cameras and other system components must be installed into confined spaces within the automobile. The new Xilinx Extensible Processing Platform offers a single-chip solution for optimizing application-specific hardware/software partitioning and accelerating functions in hardware to drive complex algorithms. This enables customers to further differentiate their embedded systems to gain a competitive advantage in their markets.

In a market expected to reach $46 billion by 2013(2), developers of new intelligent video technologies need processing platforms for building applications that can automatically monitor video patterns and body language, combined with audio, to make intelligent decisions and send alerts, thus reducing the chance for errors. The technology is already moving to full high-definition video and frame rates up to 60 frames per second, but current solutions do not offer sufficient compute power for image processing and advanced analytic functions. The dual Cortex-A9MPCore-based processor system, coupled with the massive parallel-processing capabilities of the programmable logic, enables this capability. Developers also gain an opportunity for innovative algorithm design, scalability and field upgradability within a familiar ARM-based design environment.

Wireless telecommunication is being driven by the need for lower power, smaller physical form factors and reduced development costs, to support an ever-increasing number of users and data-hungry applications. New technologies such as 4G LTE (Long-Term Evolution) can address bandwidth requirements, but smaller, more efficient base stations are essential to meeting overall market requirements. The Xilinx Extensible Processing Platform will help developers of next-generation wireless base stations to meet these needs by providing high-bandwidth parallel processing of 4G signals in combination with multiuser data management on Cortex A9 processors - all in a small, power-efficient, cost-effective integrated solution. Because the platform is extensible, developers have the flexibility to implement future equipment updates and performance upgrades of both hardware and software.

The new Extensible Processing Platform is part of Xilinx's Targeted Design Platform strategy, which provides customers with market- and application-specific environments that are easy to use, enabling them to evaluate and understand technology, and finally provide application platforms that can be modified and extended to accelerate their development time and focus on differentiation. Xilinx has also engaged with ARM Services to provide detailed ARM Cortex-A9 hardware training for design teams and field application engineers who will be supporting the eventual product rollout.

Visit the Xilinx booth (#1716) at the Embedded Systems Conference to see and learn more. Pricing and availability will be announced for products based on the Extensible Processing Platform architecture in early 2011. Visit www.xilinx.com/technology/roadmaps and click the link to "Be the First to Know" for product details, as they become available.

About Xilinx

Xilinx is the world's leading provider of programmable platforms, with more than 50 percent market share in the programmable-logic device (PLD) segment of the semiconductor industry. For more information, visit www.xilinx.com.

#1023P

XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

(1) Intelligent Car Initiative- Europe's Information Society; International Organization of Motor Vehicle Manufacturers; http://www.worldometers.info/cars/

(2) Multi-media Intelligence Report - April 2008

    Editorial Contact:
    ------------------
    Bruce Fienberg
    Xilinx, Inc.
    408-879-4631
    bruce.fienberg@xilinx.com

SOURCE Xilinx, Inc.

Copyright (C) 2010 PR Newswire. All rights reserved.

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출처: http://www.marketwatch.com/story/xilinx-unveils-arm-based-processing-architecture-for-delivering-unrivaled-levels-of-performance-in-embedded-systems-2010-04-27?reflink=MW_news_stmp

Xilinx hardwires Cortex-A9 MPCore processor into FPGA

Richard Wilson
Tuesday 27 April 2010 22:01

Xilinx has introduced its first FPGA design platform with an embedded ARM Cortex-A9 MPCore processor.

Xilinx has worked with ARM for over a year to allow the programmable logic elements of the FPGA, with their highly parallel architecture, to be closely coupled with the processor system through the AMBA-AXI on-chip bus.

According to the FPGA supplier, this architectural approach “addresses common performance bottlenecks between these parallel and serial computing environments, memory and I/O.”

“It also gives the processor system configuration control of the programmable logic, including dynamic reconfiguration,” said Xilinx.

“By creating an architecture within a familiar ARM processor-based development framework, this new Extensible Processing Platform can be the engine of innovation for many design teams held back today by performance bottlenecks,” said Vin Ratford, Xilinx senior v-p for worldwide marketing and business development.

The processor subsystem is based around ARM’s dual-core Cortex-A9 MPCore processors, each running at up to 800MHz.

The aim has been to offer within the FPGA a full processor system including caches, memory controllers and commonly used connectivity and I/O peripherals.

Efforts have also been made to support different operating systems such as Linux, Wind River’s VxWorks and Micrium’s uC-OSII.

The aim is to allow developers to tap into off-the-shelf open-source and commercially available software component libraries.

“Because the system boots an OS at reset, software development can get under way quickly within familiar development and debug environments using tools such as ARM’s RealView development suite and related third-party tools, Eclipse-based IDEs, GNU, the Xilinx Software Development Kit and others,” said Xilinx.

The AMBA-AXI bus protocol has been redesigned to make it compatible with highly parallel embedded FPGA design. It adds support for longer bursts which will support devices with large block transfers.

There is also quality of service (QoS) signalling to manage latency and bandwidth in complex multi-master systems.

“This will take embedded system design to performance and efficiency levels considered the exclusive domain of desktop, laptop and network equipment,” said Keith Clarke, v-p and general manager of fabric IP processor division at ARM.

The first FPGAs based on what the company is calling the Extensible Processing Platform will be available next year.

See: Xilinx brings ARM Cortex and AMBA to its FPGAs

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출처: http://www.electronicsweekly.com/Articles/2010/04/27/48499/xilinx-hardwires-cortex-a9-mpcore-processor-into-fpga.htm

NEWS ANALYSIS - Xilinx puts ARM core into its FPGAs

New embedded systems architecture employs ARM core in processor-centric FPGAs.

By Richard Nass

Embedded.com

(04/27/10, 05:00:00 PM EDT)

My first reaction was, "It's about time." My second reaction was, "I hope they did it right." Let me explain. Xilinx, considered by many to be the market leader for FPGAs, had a hole in its lineup, at least in my eyes. For at least a couple of years, I asked the folks at Xilinx why they weren't making a serious run at ARM-based FPGAs.

I learned that it wasn't as simple as dropping the core into the company's library. There were It actually took some design issues that needed to be overcome to ensure that the ARM core could operate at its maximum efficiency. Those changes were put in place last fall, when Xilinx announced a technology agreement with ARM.

Essentially, the technology agreement revolved around changes made to the AMBA bus to keep the programmable logic tightly coupled with the processor core. Xilinx adopted ARM physical IP, and the two companies made a technical commitment to work together to define the AMBA 4 specification, which is the de-facto industry standard for on-chip communications on SoCs designed with an ARM core.

With that technology in place, it was clear where Xilinx was headed. However, there were a few details on which Xilinx remained mum. As of today at the Embedded Systems Conference Silicon Valley, that silence is broken and all questions are being answered. They're calling it their Extensible Processing Platform that takes advantage of ARM's dual-core Cortex-A9 MPCore processors, each running at up to 800 MHz. With the platform, designers can apply a combination of serial and parallel processing for applications that require high-speed access to real-time inputs, high-performance processing, and/or complex digital signal processing.

Thanks to the changes made in the architecture, a software-centric development flow is enabled by the processor-centric approach which presents a full processor system. This includes caches, memory controllers, and commonly used connectivity and I/O peripherals. It's built using Xilinx's high-performance, low-power 28-nanometer technology.

The high-bandwidth AMBA-AXI interconnects keep the programmable logic tightly coupled with the processor core. This architectural approach addresses common performance bottlenecks between these parallel and serial computing environments, memory, and I/O. It also gives the processor control of the programmable logic, including dynamic reconfiguration.

The architecture abstracts a lot of the hardware burden from software developers, who can now tap into the vast off-the-shelf open-source and commercially available software component libraries. Another key feature is the FPGA's ability to boot an operating system (OS) at reset.

Pricing and availability will be announced for products based on the Extensible Processing Platform architecture in early 2011.

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출처: http://www.embedded.com/products/integratedcircuits/224600510

Dust Networks Announces ARM Cortex-M3 Processor Based IEEE 802.15.4 SOC

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Dust Networks Announces ARM Cortex-M3 Processor Based IEEE 802.15.4 SOC

New benchmark for ultra-low power wireless sensor network performance

Hayward, CA, (April 26, 2010)--Dust Networks®, the leading supplier of wireless sensor networks (WSN), today announced that its new IEEE 802.15.4 products will include the powerful, low power ARM®Cortex™-M3 processor. Dust Networks' new family of system-on-chips (SoCs) will be the basis for a variety of upcoming standards-based WSN products, including IEC 62591 (WirelessHART™), 6LOWPAN (IP), and Zigbee ®PRO products that will provide unprecedented low power consumption while delivering a compelling set of energy saving, high performance features including:

• A 32-bit ARM Cortex M3 processor and rich interfaces enable a powerful computing platform while conserving power.
• The world's lowest power IEEE 802.15.4 radio: a new benchmark is set, with a mere 3 mA transmit at 0 dBm and 3 mA receive current, delivering 5-10 times the battery life of competing technologies, and further expanding the applicability of energy harvesting power sources.
• Extended range capabilities, with up to 8 dBm output power on-chip PA and an optional external power amplifier.
• The industry's first IEEE 802.15.4E-ready product, incorporating the emerging standard for time synchronization and channel hopping, while providing legacy support for 802.15.4-2006.

"Our new SoCs are geared to deliver the highest performance while running at a fraction of the power of competing silicon," said Dr. Kris Pister, Chief Technologist at Dust Networks. "In selecting the ARM Cortex-M3 processor for our SoC, we did not have to trade-off performance for power. Dust Networks new IEEE 802.15.4 SoCs will require less than one-tenth of the energy per operation of comparable SoCs."

The level of systems integration in the SoCs is very high, including on-chip power amplifier, DC-to-DC converter, 10 bit ADC and a built in temperature sensor. With configurations up to 512kB of flash and 72kB of RAM, these SoCs will have both the highest computational horsepower of any 802.15.4 chip on the market, and the lowest power consumption. In doze mode, with full processor state and RAM retention, current consumption is under 1uA.

"Dust Networks' adoption of the ARM Cortex architecture is a clear demonstration of the growing support for ARM Cortex-M3 processor-based for low-power applications " said Eric Schorn, VP marketing, Processor Division, ARM. "The ARM Cortex-M3 CPU is ideal for battery operated or energy harvesting designs where performance really matters and the feature-filled Dust SoC is a powerful example of what can be done with a 'green' approach to SoC design, in applications where every nanoamp counts. "

"Low power radios such as IEEE 802.15.4 and wireless mesh networking, epitomized by Dust Networks' TSMP protocol and its "Smart Dust" roots, have transformed the industrial wireless sensor network landscape" said Mareca Hatler, ON World research director. "With the introduction of ultra low power versions of SmartMesh IP (6LoWPAN) systems and ZigBee products, Dust Networks will expand the growing number of "Smart World" applications that span Smart Buildings, Cities, Government and Homes."

About Dust Networks

Dust Networks, the leader in standards-based intelligent wireless sensor networking (WSN), provides ultra low-power, highly reliable systems to OEMs. Dust Networks wireless technology enables unprecedented access to information from the physical world, in markets that range from industrial monitoring and control to emerging markets such as the Smart Grid, Smart Cities and Smart Buildings. Dust Networks' embedded products combine extremely low-power RF System-on-Chip (SoC) technology with revolutionary wireless networking capabilities, providing OEMs with a full range of standards-based WSN solutions that are flexible and easy to integrate. Dust Networks partners with industry and standards groups such as the HART Communication Foundation, IEEE, IETF, IPSO, ISA, SunSpec Alliance and the Zigbee Alliance to ensure the broad adoption of interoperable wireless sensor networking products.

About ARM:

ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes 32-bit RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com

All material on this site Copyright © 2009 Design And Reuse S.A. All rights reserved.

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출처: http://www.design-reuse.com/news/23242/arm-cortex-m3-processor-ieee-802-15-4-soc.html

[2/23, ARM] 고성능 디지털 신호 제어용 동급 최고 Cortex-M4 프로세서 출시

고성능 신호 처리와 업계 최고 MCU 기술의 강력한 결합으로 급속하게 성장하는 하이브리드 DSC 시장 공략

ARM (한국대표: 김영섭)은 오늘 첨단 MCU(마이크로컨트롤러) 애플리케이션을 위한 혁신적인 Cortex(코어텍스)™-M4 프로세서를 출시한다고 발표했다. Cortex-M4 프로세서는 업계 최고인 ARM® Cortex-M 프로세서 제품군의 장점을 유지하면서 동시에 디지털 신호 제어(DSC: Digital Signal Control) 애플리케이션에 고효율의 솔루션을 제공한다.

특히 새롭게 부상하고 있는 모터 제어, 자동차, 전력 관리, 임베디드 오디오 및 산업 자동화 시장용 플렉서블 솔루션(flexible solution)의 요구사항을 충족하기 위해 고효율 신호 처리 기능과 Cortex-M 프로세서 제품군의 특징인 초저전력, 저비용, 사용 편리성 등이 완벽하게 결합되었다.

Cortex-M4 프로세서는 단일 사이클 MAC(Multiply-Accumulate) 장치, 최적화된 SIMD(Single Instruction Multiple Data)장치, 포화 산술연산 명령어(Saturating arithmetic instructions) 그리고 옵션으로 단일정밀도(single precision) 부동소수점처리장치(FPU: Floating-Point Unit)를 내장하고 있다. 이러한 디지털 신호 제어 기능은 ARM Cortex-M 프로세서 제품군의 특징인 혁신적인 프로세서 기술의 바탕 위에 구축되었다. 주요 기능으로는 1.25DMIPS/MHz 를 지원하는 고성능 32-비트 코어, 최적의 코드 밀도를 실현하는 Thumb(썸)®-2 명령어, 뛰어난 인터럽트 처리를 위한 NVIC(Nested Vector Interrupt Controller) 등이 있다. 이외에도 프로세서 동작의 유연성 증대를 위해, MPU(Memory Protection Unit), 저비용 디버그/트레이스 및 통합 수면 상태(integrated sleep states) 등과 같은 기능도 포함되어 있다. 임베디드 개발자들은 최대 성능과 극도로 낮은 전력 풋프린트를 가진 강력한 최종 제품을 신속하게 개발 및 제공할 수 있게 될 것이다.

디지털 신호 처리(DSP) 기술 기반의 시장을 분석하는 최고의 시장조사기관인 포워드 컨셉(Forward Concepts) 회장인 윌 스트라우스(Will Strauss)는 “임베디드 시장에서 신호 처리에 대한 요구가 전용 프로세서에서 하이브리드 마이크로컨트롤러로 바뀌고 있다. 이러한 제품들은 최고 수준의 디지털 신호 제어 기능을 구현하면서 다른 처리 연산을 효율적으로 수행할 수 있는 유연성도 동시에 제공한다”면서 “최적의 디지털 신호 제어 처리에 필요한 모든 기능과 Cortex-M 제품군 프로세서의 검증된 저전력 성능이 결합된 Cortex-M4프로세서 출시로 ARM의 파트너사들은 이러한 변화 추세를 십분 활용하게 될 것”이라고 말했다. 

Cortex-M4 프로세서는 물리적 구현을 위한 가장 폭넓은 파운드리 및 기술 지원을 제공하는 ARM 피지컬 IP 포트폴리오의 지원을 받는다. 여기에는 초 저전력 구현을 목표로 하는 파트너를 위한 TSMC CE018FG(180ULL) 공정용 Cortex-M Low Power Optimization Package (저전력 최적화 패키지)도 포함된다.

고성능 MCU 급 장치를 목표로 하는 파트너들을 위해서는 ARM은 주요 파운드리 공정에 관한 피지컬 IP 솔루션도 제공한다. 차세대 MCU 장치에서 150MHz를 목표 주파수로 하는 경우에는 65nm 글로벌파운드리(GLOBALFOUNDRIES) 65LPe 공정용 ARM 피지컬 IP를 이용하면, 65K 이내의 게이트와 40µW/MHz 이하의 동적 전력 소모를 보이는 Cortex-M4 프로세서 표준 구현이 가능하다. FPU를 포함할 경우는 25K 개의 게이트만 추가하면 되며, 이를 통해 업계 최고의 면적 풋프린트 이내에서 가장 강력한 구현이 가능하다.

SIMD와 FPU용으로 확장된 업계 표준의 ARM 컴파일러를 포함한 Keil(카일)™ MDK-ARM (마이크로컨트롤러 개발 키트)를 통해 Cortex-M4 프로세서용 개발 툴 지원이 제공된다. MDK-ARM은 µVision®4와 완벽한 Cortex-M4 프로세서 명령 시뮬레이션과 함께 첨단 트레이스 기능을 통한 타겟 디버깅도 포함하고 있다.

또한, ARM 아키텍처를 기반으로 하는 제품과 관련하여 설계에서 제작까지 완전한 솔루션을 제공하기 위해 제휴한 기업들로 구성된 업계 최대 규모의 에코시스템인 ARM Connected Community(커넥티드 커뮤니티)™회원사의 개발 툴, 디버거, RTOS 등도 Cortex-M4 프로세서를 지원한다. (세부사항은 아래 참조).

CMSIS (Cortex Microcontroller Software Interface Standard)

Cortex-M4 프로세서는 Cortex-M 프로세서 시리즈를 위한 벤더에 비종속적인 하드웨어 추상 레이어(vendor-independent hardware abstraction layer)인 CMSIS(Cortex Microcontroller Software Interface Standard)에 의해 완벽히 지원된다. CMSIS는 주변장치와 실시간 운영 시스템(RTOS)용 프로세서에 일관되고 단순한 소프트웨어 인터페이스를 구현해준다.

ARM은 현재 CMSIS를 확대하여 Cortex-M4 프로세서 확장 명령어에 대한 C 컴파일러(Compiler)지원과 MCU사용자들을 위해 신호 처리 프로그램을 쉽게 만들어주는 최적화된 라이브러리를 포함하려고 한다. 이 라이브러리에는 디지털 필터 알고리즘과 수학, 삼각법, 제어 함수 등과 같은 일반 함수가 포함될 것이다. 디지털 필터 알고리즘은 필터 설계 유틸리티와 MatLab(매트랩) 및 LabVIEW(랩뷰) 와 같은 설계 툴 키트와 함께 사용하도록 되어 있다.

이외에도, ARM은 Cortex-M4 하드웨어 및 소프트웨어에 관한 일련의 교육 코스를 개발했다. 이 교육 코스는 프로세서 출시와 함께 제공되어 라이선스 업체들이 Cortex-M4프로세서를 자신의 설계에 효율적으로 통합하고 최소한의 위험과 가장 빠른 시장 출시시간으로 최대 시스템 성능을 구현할 수 있도록 지원 할 것이다.

NXP, ST마이크일렉트로닉스(STMicroelectronics), 텍사스 인스트루먼츠(Texas Instruments) 등을 포함해 5개 주요 MCU 반도체 회사들이 Cortex-M4프로세서의 라이선스를 취득했다.

NXP 반도체의 마이크로컨트롤러 제품 라인(Microcontroller Product Line) 본부장인 조프 리스(Geoff Lees)는 “본사의 ARM Cortex 포트폴리오에 ARM Cortex-M4프로세서가 추가됨으로써 본사의 Cortex-M3 와 Cortex-M0 프로세서 기반 장치를 보완하게 되었으며, MCU 커뮤니티에 엔드-투-엔드 솔루션을 제공할 수 있게 되었다”고 말하면서 “Cortex-M4 프로세서는 이제 새로운 수준의 마이크로컨트롤러를 구현하여 신호 처리 시장의 고성능, 저전력 요구를 충족한다”고 덧붙였다.

ST의 마이크로컨트롤러 사업부문의 32-비트 마케팅 매니저인 세미르 하다드(Semir Haddad)는 “Cortex-M4 프로세서 도입으로 집약적인 수학 연산을 요구하는 애플리케이션까지 Cortex-M코어 사용을 확대 할 수 있게 되었다”면서 “Cortex-M4 프로세서 기반의 제품 라인이 본사 STM32마이크로컨트롤러 라인을 보완하여 본사 고객들은 STM32 확장성과 고급 신호 처리 기능을 결합할 수 있게 되었다”고 말했다.

텍사스 인스트루먼츠의 전세계 스텔라리스(Stellaris®) MCU 마케팅 총괄인 쟝 앤 부스(Jean Anne Booth)는 “Cortex-M4 프로세서는 PID 루프를 생성하며 상위 레벨의 모션 컨트롤을 향상시키고 더욱 신뢰할 수 있게 해줄 뿐 아니라 개발자들이 효율적인 모터 제어로 매우 높은 에너지 절감을 실현할 수 있게 한다”며, “또한 랩뷰나 매트랩/시뮬링크와 같은 메타 랭귀지 툴을 사용하는 비-프로그래머(non-programmer) 들도 ARM MCU 사용에 제한이 없게 되었다. 추가로, 내추럴/네이티브 C와 C++ 애플리케이션도 사용가능하여, 워크스테이션/전화/일반 임베디드 프로세서와 딥 임베디드 시스템에서 동일한 알고리듬을 사용함으로써 개발 시간과 위험을 줄일 수 있다”고 덧붙였다.

ARM의 프로세서 사업 부문 마케팅 부사장인 에릭 숀(Eric Schorn)은 “ARM이 본사 프로세서 제품에 DSP 기능을 포함시키기 시작한지 어느 정도 시간이 지났으며, 애플리케이션 시장에서 굉장한 성공을 거두어 왔다. 그러나 딥 임베디드 장치용으로 디지털 신호 제어 기능을 갖춘 프로세서를 설계 한 것은 이번이 처음”이라면서 “Cortex-M4 프로세서는 모터 컨트롤, 의료 기기, 자동차에서 산업 자동화, 전력 관리, 오디오 애플리케이션에 이르기까지 점점 늘어나는 임베디드 애플리케이션의 늘어나는 신호 처리 요구를 충족하기 위해 설계되었다”고 밝혔다.

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출처: http://www.semiconnet.co.kr/news_read.asp?seno=6828

NXP Semiconductors debuts LPC1340 with USB 2.0.

New microcontroller family based on ARM Cortex-M3
Loring Wirbel, Contributing Editor -- EDN, 12/7/2009 10:12:00 AM

NXP Semiconductors Inc. has introduced the latest member of its ARM-based microcontroller family, the LPC1340. The Cortex-M3 RISC core is combined with a full USB 2.0 device controller, complete with drivers certified by USB-IF. The chip includes a USB PHY and an 8-channel, 10-bit A/D converter.

The LPC1340 can be configured with up to 32 Kbytes of flash and 8 Kbytes of SRAM. External interfaces include UART, SPI controller, and I2C, and the device offers up to 42 general purpose I/O pins. The USB controller supports four transfer types, including isochronous, a necessity for real-time multimedia and audio applications. USB drivers, implemented in ROM, support Mass Storage Class (MSC) and Human Interface Device (HID) class. Price in quantities of 10,000 starts at $1.49 each.

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출처: http://www.edn.com/dev-monkey/article/CA6710239.html?nid=2437&rid=8803234