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2006년 6월 13일 화요일
Emailing: Display Resolution
2006년 6월 2일 금요일
Power Management DesignLine | How you can manage multiple voltages in portables
How you can manage multiple voltages in portables
Typically, DC-DC converters are specified to meet ±2% initial setpoint accuracy and 3% over input voltage, loading and temperature conditions until end of life. This is insufficient for performance, testing and reliability reasons. Device voltage levels for multi-voltage Processors, DSPs and ASICs have fallen to 0.9V and are approaching 0.6V, making system voltage tolerances tighter and necessitating a new way to keep these voltage levels within specifications. If these requirements are not followed, performance degradation, fault conditions such as bus contention or device latch-up can arise. This article describes the importance of accurate DC output voltage control and a method to actively control any standard adjustable DC-DC converter module, discrete DC-DC PWM controller or LDO over time and temperature. A reference design using a standard Point-of-load (POL) DC-DC converter footprint and discrete switching regulator is shown with extremely accurate ±0.2% output levels. The POL automatically adjusts supply output voltage levels under all DC load conditions with programmable supply voltage margining allowing in-system test and control. A programmable 9-channel power supply PWM controller design is shown exhibiting ±0.5% accuracy. It forms a complete portable power system under digital control allowing dynamic adjustment of output voltage levels.
The need for accuracy and programmability As processor supply levels drop, both input current and voltage accuracy requirements increase. For this reason, systems are migrating from isolated distributed power to non-isolated distributed power architectures using POL solutions to gain improved voltage regulation and control at the load (Figure 1). Isolated distributed power uses 2 or more -48V isolated step-down DC-DC converters, which then route separate lower voltage supplies across the board. In the point of load distributed architecture, the -48V powers a single isolated DC-DC converter to provide an intermediate bus voltage. This intermediate bus voltage then powers many non-isolated DC-DC converters or LDO's at the load as shown in Figure 1.
Figure 1 -- An example card design with power management functions necessary in data communications systems. These functions include Hot Swap, Supply Cascading/Sequencing and Tracking, Environmental Monitoring and Reset Control. As component power requirements change, the power management device can be in-system programmed using the I2C bus. The power supply is bussed from a main power bus and down converted directly at the load.
This architecture is more desirable because components making up the heart of the line card require lower voltages and higher currents and regulating at the load reduces inaccuracies. Power Management controllers are included to turn on/off and continuously monitor the POL supplies. Providing power at the load gives superior regulation, transient response and avoids voltage drops across PCB traces. This is necessary because as voltage levels decrease, allowable supply variations around these levels also decrease. Devices now not only require specific power supply turn on sequencing, but they also run at 1V or lower levels. These tighter limits demand more accurate control especially under changing load conditions and temperature variations to maintain optimal performance. The power system must automatically adjust and also test the limits of each board to guarantee performance and reliability. A highly integrated and accurate power supply manager, monitor and sequencer can achieve this required performance.
Processors are being marketed with various operating frequencies. For example, a processor with an operating frequency of 300MHz and a processor from the same manufacturer with an operating frequency of 700MHz are not fundamentally different. In fact, the 300MHz processor is not designed to run at 300MHz, it simply failed to perform to specification at 700MHz. Any processor manufacturer's data sheet will show that the higher performing processors are the result of processors yielding over a more stringent power supply rating.
The tighter power supply tolerances dictated by the high performance processor manufacturers have placed a heavy burden on the system designer. Typically, a processor's power supply tolerance is ±2.5%, which is ±25mV for a 1V supply. This power supply tolerance needs to be maintained over the full operating temperature of the board. When these challenges are compounded with board layout issues such as voltage drops across the power traces, board designers can find themselves in a desperate situation with a looming deadline.
There are several factors that affect the accuracy of a power supply. Take for example the standard structure of the non-isolated DC-DC converter shown in Figure 2. The resistor divider created by R1 and R2 sets the output voltage of the converter by feedback to the error amplifier against the reference voltage. This feedback keeps the inverting input terminal of the error amplifier and therefore the output of the supply equal to the converter's reference voltage. Inaccuracies in resistors R1 and R2 will cause errors in the set point of the converters output voltage. Variations in these resistors over temperature will increase the cumulative error. Errors in the converter's reference voltage also causes inaccuracy of the output voltage. Board layout can also decrease the accuracy of the DC-DC converter. Improper placement of the converter's voltage sense lines can result in uncompensated power trace IR losses to the load point.
Active DC Output Control
Active DC Output Control (ADOCTM) is one method of accurately controlling the output of a DC-DC converter or LDO to achieve high accuracy power supply voltages. Active DC Output Control is a new approach to intelligent power management. Using ADOC a designer can control the output of DC-DC converters or LDOs to ±0.2% for applications involving high performance processors. ADOC controls the output of a converter by effectively adjusting the resistors that set the output voltage of either a DC-DC converter or adjustable LDO. An ADOC solution is typically connected to a DC-DC converter as shown in Figure 2. The ADOC circuit stores the desired output voltage as a digital 10-bit value in non-volatile memory. The ADOC circuitry monitors the converters output at the load. After significant filtering and signal conditioning, the converter's output is compared to an inexpensive reference voltage accurate to ±0.1%. A decision is then made to increase or decrease the control signal to adjust the converter's output to the desired voltage ±0.2%.
Figure 2 " The ADOC connection to a standard DC-DC converter. The ADOC function Controls DC-DC Converters via the TRIM pin. The CTRIM_CAP and RTRIM component type and values are determined for optimal operation. The RTRIM resistor is not necessary for DC-DC converter modules employing an on-board Trim Resistor.
The Output voltage in Figure 2 is derived from the following equations:
Eq1...
Eq2...
Where: 0.3 = TRIM output saturation voltage
and Vnom = Nominal non-trimmed output voltage
One problem with attempting to control the output voltage of a power supply is the possibility of interfering with the power supply's feedback control loop. Using two control loops is inherently risky and sometimes results in system instability. ADOC, however, uses a system of nonlinear, inherently convergent control to maintain system stability when coupled with the converter's control loop. The control loop of a DC-DC converter is optimized for fast transient response. On the other hand, the goal of ADOC is to accurately control the DC or average level of the output voltage. For controlling the DC voltage level the ADOC control loop runs very slow at 500Hz whereas the converters control loop responds to frequencies in the tens to hundreds of kHz. This large separation of loop response alone however does not guarantee system stability. The ADOC control loop employs a nonlinear digital control element where the adjustment to the output is always of the same magnitude. This nonlinear control induces a very small ripple voltage on the converter's output voltage. For any noise in the system with a magnitude greater than this induced ripple the gain of the ADOC control loop is less than 1. For noise of magnitude less than the induced ripple the gain is greater than 1. This noise is amplified until its magnitude is greater than the induced ripple where the loop then has a gain of less than 1. This sequence is referred to as a stable limit cycle in nonlinear systems. The induced ripple can be set with the ADOC circuit to less than 100μVp-p thus rendering it negligible.
The ADOC circuit is superior to simply using higher accuracy components such as the feedback resistors and the voltage reference for several reasons. The ADOC circuit actively controls the power supply's output so changes in temperature that affect the components of the converter result in only the ultra-low temperature variation associated with the ADOC circuit itself. Also, through the use of non-volatile memory to set the output voltage, ADOC can be used to voltage margin a converter's output accurately. This margining is a common practice among board designers to determine the robustness of a design by subjecting the board to the various voltage ranges. Some products use voltage margining as a production test to ensure system reliability. A returned board from the field is costly. Given this, companies are fearful of having marginal components on their boards. This has resulted in mandates for voltage margin testing every board that is manufactured.
The mechanism of supply margining is the same as that of supply controlling: adjust and hold the DC value of the supply. So naturally, ADOC also benefits voltage margin testing. If a mandate is set to margin test boards to ±10% with supplies that are only accurate to ±4%, the results can be unpredictable. For instance, are the supplies being margined to ±6% or are they margined to ±14%? In the 6% case the reliability test is ineffective. In the 14% case, a class of boards could be subject to yield or failure loss and the false positives result in longer debug times. Using ADOC to margin voltages in these tests increases the confidence of the test because it is well known how close the testing is to the margin limits.
The margin function can also be used for performance enhancement or to digitally control brightness by adjusting white LED backlights or contrast on an LCD as well as volume levels in an audio circuit.
The converter may be an off-the shelf compact device, or may be a "roll your own" circuit residing on the system board. In either case, the Active DC Output Control function dramatically improves voltage accuracy by implementing closed-loop active control. This utilizes the DC-DC's Trim pin as shown in Figure 2 or an equivalent output voltage feedback adjustment "VADJ" or "FB" node in a user's custom circuit.
To prove the ADOC concept, a non-isolated power supply reference design is shown in Figure 3. It is a fully functional POL DC/DC converter board used to demonstrate the improvement of using a digitally programmable nonvolatile supply voltage marginer and ADOC controller. The reference design operates from a +3.3V to +5V input and includes a synchronous PWM DC-DC converter, n-channel MOSFETs, and high current inductor. A precision voltage reference internal to the ADOC integrated circuit permits the DC-DC converter to be trimmed to within a 0.2% tolerance. The power management device controls the voltage monitoring, margining and trimming of the DC-DC PWM buck controller. Voltage margining along with many other programmable features are performed through the I2C 2-wire bus and Windows GUI interface (Figure 4). The key details of the design are the 16A Output Current with internal VREF, extremely accurate (±0.2%) control automatically adjusts supply output voltage level under all DC load conditions. A wide Margin/ADOC range from 0.3V to VDD with 2 programmable general purpose monitor sensors -- UV and OV with FAULT Output Flag, monitoring status and 256 Byte EEPROM, programmable nominal, high and low trim/margin voltages.
click to enlarge
Figure 4 -- Windows GUI used to program and control the POL Reference design. All voltage levels and triggers are programmable using a Windows GUI and a PC-compatible parallel port to I2C serial bus programmer. Power management design is simplified using non-volatile programmable functions, when power is removed all settings are remembered.
Supply control using a programmable PWM controller for portable or handheld systems
To further standardization, a programmable supply voltage sequencing platform provides advantages over fixed solutions. One advantage is that a programmable solution reduces risks over changing system requirements. With a programmable solution the sequencing order can be modified and sequenced channels can be changed by simply reprogramming the controller. This minimizes the potential for having to re-spin the board when the system requirements are not clearly understood. A programmable solution also gives the designer more confidence that the board will work the first time. If a problem is encountered, reprogramming can get past the problem and onto debugging and testing the board for its intended function. On a company wide basis, the programmable solution also allows for cross platform implementation where an existing design can be reused for a unique solution by simply reprogramming.
A fully programmable power supply with integrated PWM controllers that monitors, margins, and cascade sequences provides all the power management needed in a power system. To provide a complete system, 9 voltage outputs plus voltage reference, consisting of: four synchronous PWM "buck" step-down converters, three PWM "boost" step-up converters, one PWM "boost-buck" negative DC/DC converter, and an LDO.
Figure 5 -- Typical portable power management schematic using a 9-channel, programmable DC/DC controller. This integrated supply controller/manager provides power-on/off control, cascade sequencing and output margining.
The power system is capable of power-on/off cascade sequencing where each channel can be assigned to one of 8 unique sequence positions. Supplies may also be individually powered on/off through an I2C command or by assertion of one of two enable pins. Cascade sequencing, unlike time based sequencing, uses feedback to ensure that each output is within specification before the next channel is enabled.
Each output voltage and the input voltage or battery is monitored for under-voltage and over-voltage conditions. In the event of a fault, all supplies may be sequenced down or immediately disabled. Multiple output status pins are provided to notify host processors or other supervisory circuits of system faults. An Undervoltage Lockout (UVLO) circuit ensures the controller will not power up until the input or battery voltage has reached a safe operating value. The UVLO function exhibits hysteresis, ensuring that noise on the supply rail does not inadvertently cause faults or otherwise compromise the control of the output supplies.
In the event of a system fault, all monitored supplies may trigger fault actions such as power-off, or forced-shutdown operations. Each supply output may also be turned off individually at any point using the I2C command or one of two programmable enable pins.
In portable applications powered from a main system battery the battery voltage is continuously monitored for under-voltage conditions. There are two under-voltage settings for the battery; both are user programmable and have a corresponding status output pin. When the first threshold level is reached, the POWER_FAIL pin is asserted and latched. When the second threshold level is reached on the main supply, the nBATT_FAULT pin is asserted.
Voltage margin control of all output voltages through an I2C command by at least ±10% of the nominal output voltage is included. Margining creates three pre-programmed voltage settings that each channel can be set to via an I2C command. Margining is ideal when used with a channel configured as an LED driver where margining provides three brightness settings. In addition, each output is slew rate limited by digital soft-start circuitry that is user programmable and requires no external components.
All programmable settings are stored in non-volatile registers and are easily accessed and modified over an industry standard I2C serial bus. For quick prototype development Summit offers an evaluation card and a Graphical User Interface (GUI).
Figure 6 - Power-on Cascade sequencing and Margin High/Low Waveforms. The supply channels are cascade sequenced-on to nominal voltage, margined high or low and then cascade sequenced-off. Channels 1, 2, 3, 4 are first margined high and then channels 2 and 3 are margined low. Up to 8 PWM supplies are controlled. (Ch 1 (500mV/D) = 1.25V Buck (Yellow trace), Ch 2 (500mV/D) = 2.5V Buck (Blue trace), Ch 3 (2V/D) = -7.5V Inverting Buck-Boost (Purple trace), Ch 4 (2V/D) = 12V Boost (Purple trace))
Conclusion
New digitally programmable power supply controller provide I2C programmable output voltages, Power on and off sequencing, Individual channel enable control, Battery monitoring, UV and OV monitoring on PWM outputs, Margining and Slew rate control. Actively controlling DC output voltage levels to within ±0.2% under light or full load to meet stringent tolerance requirements of high performance components further extends reliable operation and margining supplies tests system performance goals as well as providing an easy way to adjust brightness and volume control. The integration of active accuracy control, programmable features and built-in flexibility allows the system designer to create a "platform solution" that can be easily modified via software without major hardware changes. Combined with re-programmability, this facilitates rapid design cycles and the proliferation from a base design to future generations of product.
About the Authors:
Tom DeLurio is director of applications engineering at Summit Microelectronics. He is responsible for supporting customer implementation of Summit devices, evaluation kit production and new product definition. Before joining Summit, Mr. DeLurio held applications engineering management positions at Impala Linear Corporation. He has also held positions at Micro Linear Corporation, Aspen/Cypress Semiconductor, NCR Corporation's ASIC division, Honeywell, and Signetics Corporation. Mr. DeLurio has authored numerous articles for industry publications. He holds a BSEE degree from Pennsylvania State University. tom_delurio@summitmicro.com
George Hall is Staff Applications Engineer at Summit Microelectronics. He is responsible for supporting customers using Summit devices, evaluation kit design and new product definition. Before joining Summit, Mr. Hall was an applications engineering at Monolithic Power Systems. He has also held positions at Micro Linear Corporation, Micrel Semiconductor, Raynet, Computer Products, and General Electric. Mr. Hall has authored numerous application notes and holds a patent in phase-locking switched-mode power supplies. ghall@summitmicro.com
2006년 4월 27일 목요일
All about FPGAs
March 21, 2006
All about FPGAs
An industry expert examines field-programmable gate arrays (FPGAs), including current and forthcoming architectures, technologies, and software tools.
By Bob Zeidman
This article examines field-programmable gate arrays (FPGAs) and their underlying architectures and technologies. We will also examine current and up-and-coming software tools that are designed to allow you to squeeze more functionality into these chips in less time, running at faster speeds, and using less power.
Introduction
The first section of this article deals with the internal architecture and characteristics of typical FPGA devices, allowing you to decide which particular device is right for your design. The next section examines new FPGA architectures being offered by various vendors. The final section looks at some new software tools to help you with your designs.
The basics of FPGAs
Field-programmable gate arrays (FPGAs) are so-called because they are structured very much like the now-obsolete "gate array" form of application specific integrated circuit (ASIC). In fact, FPGAs essentially killed the gate array ASIC business. In the not-so-distant past, FPGAs were marketed for primarily two uses: (a) for prototyping ASICs and (b) for use in systems to achieve time-to-market knowing that they would be replaced with an ASIC implementation at the earliest opportunity.
With regard to this latter point, FPGAs can be programmed on your desk top in minutes while ASICs require weeks to fabricate a new design. As FPGA speeds increased, power consumption decreased, and prices decreased, FPGAs began shipping in products without any intention of replacing them with equivalent ASICs. Of course FPGAs are still good at prototyping ASICs and they are still used that way.
FPGA architectures
Each FPGA vendor has its own FPGA architecture, but in general terms they are all a variation of that shown in Fig 1. The architecture consists of configurable logic blocks, configurable I/O blocks, and programmable interconnect. Also, there will be clock circuitry for driving the clock signals to each logic block. Additional logic resources such as ALUs, memory, and decoders may also be available. The three basic types of programmable elements for an FPGA are static RAM, anti-fuses, and flash EPROM.
1. Generic FPGA architecture.
Configurable Logic Blocks (CLBs): These blocks contain the logic for the FPGA. In the large-grain architecture used by all FPGA vendors today, these CLBs contain enough logic to create a small state machine as illustrated in Fig 2. The block contains RAM for creating arbitrary combinatorial logic functions, also known as lookup tables (LUTs). It also contains flip-flops for clocked storage elements, along with multiplexers in order to route the logic within the block and to and from external resources. The multiplexers also allow polarity selection and reset and clear input selection.
2. FPGA Configurable logic block (CLB) (courtesy of Xilinx).
Configurable I/O Blocks: A Configurable input/output (I/O) Block, as shown in Fig 3, is used to bring signals onto the chip and send them back off again. It consists of an input buffer and an output buffer with three-state and open collector output controls. Typically there are pull up resistors on the outputs and sometimes pull down resistors that can be used to terminate signals and buses without requiring discrete resistors external to the chip.
The polarity of the output can usually be programmed for active high or active low output, and often the slew rate of the output can be programmed for fast or slow rise and fall times. There are typically flip-flops on outputs so that clocked signals can be output directly to the pins without encountering significant delay, more easily meeting the setup time requirement for external devices. Similarly, flip-flops on the inputs reduce delay on a signal before reaching a flip-flop, thus reducing the hold time requirement of the FPGA.
3. FPGA Configurable I/O block (courtesy of Xilinx).
Programmable Interconnect: In Fig 4, a hierarchy of interconnect resources can be seen. There are long lines that can be used to connect critical CLBs that are physically far from each other on the chip without inducing much delay. Theses long lines can also be used as buses within the chip.
There are also short lines that are used to connect individual CLBs that are located physically close to each other. Transistors are used to turn on or off connections between different lines. There are also several programmable switch matrices in the FPGA to connect these long and short lines together in specific, flexible combinations.
Three-state buffers are used to connect many CLBs to a long line, creating a bus. Special long lines, called global clock lines, are specially designed for low impedance and thus fast propagation times. These are connected to the clock buffers and to each clocked element in each CLB. This is how the clocks are distributed throughout the FPGA, ensuring minimal skew between clock signals arriving at different flip-flops within the chip.
In an ASIC, the majority of the delay comes from the logic in the design, because logic is connected with metal lines that exhibit little delay. In an FGPA, however, most of the delay in the chip comes from the interconnect, because the interconnect - like the logic - is fixed on the chip. In order to connect one CLB to another CLB in a different part of the chip often requires a connection through many transistors and switch matrices, each of which introduces extra delay.
4. FPGA programmable interconnect (courtesy of Xilinx).
Clock Circuitry: Special I/O blocks with special high drive clock buffers, known as clock drivers, are distributed around the chip. These buffers connect to clock input pads and drive the clock signals onto the global clock lines described above. These clock lines are designed for low skew times and fast propagation times. Note that synchronous design is a must with FPGAs, since absolute skew and delay cannot be guaranteed anywhere but on the global clock lines.
SRAM vs. Antifuse vs. Flash
There are three competing technologies for programming FPGAs. SRAM programming involves a small static RAM bit for each programming element. Writing the bit with a zero turns off a switch, while writing with a one turns on a switch. Another method involves an antifuse that consists of a microscopic structure that, unlike a regular fuse, normally makes no connection. A large amount of current during programming of the device causes the two sides of the antifuse to connect. A third and relatively new method uses flash EPROM bits for each programming element.
The advantages of SRAM-based FPGAs - the most common programming technology by far - is that they use a standard fabrication process that chip fabrication plants are always optimizing for better performance. Since the SRAMs are reprogrammable, the FPGAs can be reprogrammed any number of times, even while they are in the system, just like writing to a normal SRAM. SRAM devices can easily use the internal SRAMs as small memories in the design.
The disadvantages of SRAM-based FPGAs are that they are volatile, which means a power glitch could potentially corrupt the contents of the device. SRAM devices have large routing delays and are slower than other technologies, in theory, but continually improving SRAM technology has effectively eliminated this disadvantage. SRAM FPGAs can consume more power and are less secure than other technologies because they must be reprogrammed upon power-up and the programming bitstream can be observed going into the device. Custom SRAM FPGAs with built-in keys that unencrypt incoming program bit streams can be purchased from vendors, but this reduces the low cost and fast lead time advantage of the FPGA. Bit errors are also more likely with SRAM FPGAs than with the other devices. The market has decided that the advantages of SRAM FPGAs outweigh the disadvantages as they are by far the dominant FPGA technology.
The advantages of antifuse FPGAs are that they are non-volatile and the delays due to routing are very small, so they tend to be faster. Antifuse FPGAs tend to require lower power and they are better for keeping your design information out of the hands of competitors because they do not require an external device to program them upon power-up as SRAM devices do. The disadvantages are that they require a complex fabrication process, they require an external programmer to program them, and once they are programmed, they cannot be changed. The complex, nonstandard fabrication process has turned out to be a key disadvantage as antifuse FPGAs have lower yields and the technology has improved more slowly than SRAM FPGAs.
Flash FPGAs seem to combine the best of both of the other methods. They are nonvolatile like antifuse FPGAs, yet reprogrammable like SRAM FPGAs. They use a standard fabrication process like SRAM FPGAs and they are lower power and secure like antifuse FPGAs. They are also relatively fast. Currently, one vendor supports flash FPGAs and another vendor has a hybrid flash/SRAM FPGA. They are not catching on as fast as I expected, though that could change in the future.
Example FPGA families
Examples of SRAM FPGA families include the following:
- Altera Stratix II and Cyclone II families
- Atmel AT6000 and AT40K families
- Lattice LatticeEC and LatticeECP families
- Xilinx Spartan-3 and Virtex-4 families
- Actel SX and Axcelerator families
- Quicklogic Eclipse II family
- Actel ProASIC family
- Lattice LatticeXP family
Cores: When I talk about a "core" I am simply referring to a large self-contained function. There are two basic types of cores. The soft core, known as an IP core, is a function that is described by its logic function rather than by any physical implementation. Soft cores usually consist of hardware description language (HDL) code. Hard cores, on the other hand, consist of physical implementations of a function. With respect to FPGAs, these hard cores are known as embedded cores because they are physically embedded onto the chip die and surrounded by programmable logic.
Many FPGA vendors have begun offering cores. The density of programmable devices is increasing, enabling what is called a Programmable System on a Chip (PSOC). Whereas programmable devices were initially developed to replace glue logic, entire systems can now be placed on a single programmable device. SOCs include of all kinds of complicated devices, like processors. In order to place these complex functions within a programmable device, there are three options: the first is to either (a) design the function yourself and place it in the programmable logic, (b) purchase the HDL code for the function and incorporate it into your HDL code, or (c) get the vendor to include the function as a cell embedded in the programmable device. The second option is the IP core or soft core, while the third option is the embedded core or hard core.
IP Cores: IP cores are often sold by third party vendors that specialize in creating these functions. Recently, FPGA vendors have begun offering their own soft cores. IP cores reduce the time and manpower requirements for the FPGA designer. IP cores have already been designed, characterized, and verified. Also, IP cores can often be modifiable, meaning that you can add or subtract functionality to suit your needs. They are also portable from one vendor to another.
But IP cores may also be expensive. Electrical characteristics such as timing or power consumption for IP cores can be optimized to a limited degree, but the actual characteristics depend on its use in a particular device and also depend on the logic to which it is connected. IP cores purchased from a third party may not be optimized for your particular FPGA vendor's technology. You may not be able to meet your speed or power requirements, especially after you have placed and routed it.
Embedded Cores: The embedded core is ideal for many users, which is one reason why programmable device vendors are now offering embedded cores in their devices. The embedded core will be optimized for the vendor's process to give you good timing and power consumption numbers. The function will be placed as a single cell on the silicon die and so the performance of the function will not depend on the rest of your design since it will not need to be placed and routed.
Some embedded cores are analog devices that cannot be designed into an ordinary FPGA. By integrating these functions into the device, you can avoid the difficult process of designing analog devices, and you save the chips and components that would otherwise be required outside the programmable device.
Of course there is a drawback to embedded cores. By using an embedded core in your programmable device, you tie your design into a single vendor. Unless another vendor offers the same embedded core, switching to another vendor will require a large effort and will not be pleasant.
Processor Cores: Processor cores are one of the types of cores commonly available as IP cores or embedded cores. These processors tend to be those that are designed for embedded systems since, almost by definition, programmable devices are embedded systems.
If the processor core is embedded, you will be using a processor that has been optimized and has predictable timing and power consumption. For either type of core, tools will be readily available for software development. Off-the-shelf cross compilers and simulators can be used to debug code before the design has been completed and the programmable device is available.
An example of an FPGA with an embedded processor, along with other embedded cores, is shown in Fig 5.
5. FPGA with embedded processor core (courtesy of Quicklogic).
DSP Cores: Digital Signal Processors (DSPs) are another common type of core that is offered as an IP core or an embedded core. These are essentially specialized processors that are used for manipulating analog signals. They are commonly used for filtering and compression of video or audio signals.
Many engineers have argued that as general processors become faster, DSPs will be less useful because the same functions can be accomplished using the generic processors. However, video and audio digitization, compression, and filtering requirements have increased in recent years as millions of users connect to the Internet and regularly upload and download all kinds of information over relatively limited bandwidth connections. So far, DSP demand for use in networking and graphics devices has been increasing, not decreasing.
Analog Cores: FPGA vendors have begun to include analog cores in their FPGAs. For example, PHY cores are the analog circuitry that drives networks. Many companies are now integrating this functionality onto their devices. Because these devices include specialized analog circuitry, they are available only as embedded cores.
6. FPGA with embedded PHY core (courtesy of Actel).
A functional block diagram of an FPGA that includes an embedded processor core, embedded digital peripheral cores, and embedded analog cores is shown in Fig 6.
Special I/O Drivers: Special I/O drivers are also being embedded into programmable devices. The newer buses inside personal computers need to have very tightly controlled timing and must be driven by special high-drive, impedance-matched circuits. The I/O buffers need to have inputs with very specific voltage threshold values. Many vendors now offer programmable devices with I/O that meet these special requirements. Many times, this is the only way to design a programmable device that can interface with these buses without external chips and components.
New Architectures: New basic architectures are being developed for the logic blocks that comprise FPGAs. One new architecture has a logic block that is based on a DSP, as shown in Fig 7. This type of FPGA will be better for use in chips that need a significant amount of signal processing. I have certain doubts about this future path, though. First, the majority of programmable devices do not perform any DSP, so this architecture targets a relatively small market. Second, special tools will be needed to convert digital signaling algorithms for use in such a specialized FPGA. These tools will need to optimize the algorithm very well so that performance in this specialized FPGA can actually perform better than a standard DSP, or a generic processor, running code that has been optimized using tools and compilers that have been available for years.
7. DSP core cell in an FPGA (courtesy of Altera).
New tools
The most significant area for the future, I believe, lies in the creation of new development tools for FPGAs. As programmable devices become larger, more complex, and include one or more processors, there is a huge need for tools to take advantage of these features and optimize the designs.
As FPGAs come to incorporate processors, development tools are needed for software just as much as for hardware. Hardware synthesis tools allow hardware engineers to work at higher levels of abstraction, without the need to understand the details of the underlying hardware architectures. Similarly software synthesis tools are needed to allow software engineers to work at a higher level of abstraction without the need to understand the details of the underlying software architecture.
Ultimately, there will have to be a melding of hardware and software expertise in an FPGA designer. System level issues must be understood and addressed. Future intelligent tools will work with libraries of pre-tested hardware objects and software functions, leaving "low-level" C and Verilog design necessary only for unique, specialized sections of hardware or software.
Eventually, platform FPGAs with embedded processors will become the dominant platform for embedded system design, and will finally allow the fulfillment of the promise of, and force further development of, hardware/software co-design tools.
Conclusion
This article has presented an overview of current and emerging FPGA technologies, architectures, and tools. You are now prepared to delve into your first or fiftieth FPGA design with the confidence that your knowledge is up to date and that you have the ability to accurately evaluate the various FPGA vendors and their families, and the software tools needed to ensure your design works as required.
Bob Zeidman is the president of Zeidman Technologies (http://www.zeidman.biz/), a company that develops hardware/software co-design tools. He is also president of Zeidman Consulting (http://www.ZeidmanConsulting.com/), a contract research and development firm. Among his publications are technical articles on hardware and software design methods as well as three textbooks: Designing with FPGAs and CPLDs, Verilog Designer's Library, and Introduction to Verilog. Bob holds two patents and earned bachelor's degrees in physics and electrical engineering at Cornell University and a master's degree in electrical engineering at Stanford University. Bob can be contacted at Bob@ZeidmanConsulting.com.
All material on this site Copyright © 2006 CMP Media LLC. All rights reserved
2006년 4월 25일 화요일
VHDL Syntax
- http://mikro.e-technik.uni-ulm.de/vhdl/vhdl87_syntax.html
VHDL Syntax (IEEE Std 1076-1993)
- http://mikro.e-technik.uni-ulm.de/vhdl/vhdl93_syntax.html
VHDL samples (references included)
The sample VHDL code contained below is for tutorial purposes.An expert may be bothered by some of the wording of the examplesbecause this WEB page is intended for people just starting tolearn the VHDL language. There is no intention of teachinglogic design, synthesis or designing integrated circuits.It is hoped that people who become knowledgeable of VHDL willbe able to develop better models and more rapidly meet whatevertheir objectives might be using VHDL simulations.
Verilog Coding Styles for Synthesis
Synthesizeable Verilog Code Examples
This page gives FREE synthesizable verilog code examples, block diagrams and timing diagrams of typical digital circuit building blocks.
Last update August 2000
2006년 4월 7일 금요일
uCdot | Getting Started with uClinux
http://www.ucdot.org/article.pl?sid=02/09/03/1357255
This article shows how to get started with uClinux on the Pilot and ARMulator emulators. As no hardware is needed it's a good way to get your feet dirty in uClinux.
커널 2.6 Intro
| 커널 2.6 Intro | (2006/03/21) |
커널 2.6에 대한 간략한 소개와 커널 컴파일에 대해 설명하고 있는 KLDP 위키 문서 입니다 링크만 걸어드릴게요 ^_^ |
2006년 3월 19일 일요일
2006년 3월 18일 토요일
+ Google’s services
Here’s the big list of Google’s services:
- Add to Google lets publishers create a custom “Add to Google” button for their RSS feeds. When a user clicks the button, they can choose to either add the feed to Google Reader, or the Google Homepage service.
- Blogger is Google’s blog-hosting and creation service which seems to be very popular on the web because of the price (free) and ease of use.
- Froogle is Google’s product search engine that you can use to find the cheapest price for a product.
- GMail (or Google Mail) is Google’s popular email service, that gives you over 2 gigabytes of storage.
- Google AdSense is Google’s contextual advertising service, popular among many websites. Google also released Onsite Advertiser Sign-Up on November 21, 2005 which lets advertisers buy ads on a site directly from the Google Ads on that page.
- Google AdWords is the other side of AdSense. While AdSense lets publishers put ads on their site, someone has to pay for those ads, and AdWords connects companies with publishers so you can make a little bit of money.
- Google Alerts are e-mail updates to particular searches you do on Google. Pretty useful for monitoring websites or news.
- Google Analytics crawls your website and keeps track of your visitors through a small piece of Javascript. Great tool for webmasters trying to improve their stats and AdSense revenue.
- Google Answers lets you hire someone to research a topic or answer a question for you.
- Google Base looks like its going to be Google’s massive content library, with all sorts of content, uploadable by anyone. Oddly enough, it sounds like EPIC and Google Grid mentioned in this video. Many people are comparing this service to Craigslist.
- Google Blog Search is very much like the web search service but letting search only through various blogs around the web.
- Google Book Search allows you to search though books that Google has scanned into their database.
- Google Catalogs is a search engine for mail-order catalogs.
- Google Click-to-Call lets users call advertisers directly from Google search results, for free, at Google’s expense.
- Google Code is Google’s effort to promote and contribute to Open Source software.
- Google Compute exists as a part of the Google Toolbar and uses your computer’s idle time (when you’re not using it) to compute data from distributed computing projects like Folding@Home.
- Google Deskbar is essentially an embedded IE window in your Window Taskbar that you can search Google from.
- Google Desktop is similar to apps like Konfabulator or Dashboard but not as attractive. It offers various widgets and a sidebar which let you do things like searches, aggregate feeds, write notes, check weather, and more.
- Google Directory which is similiar to Yahoo’s and dmoz’s services, letting you search by category.
- Google Earth is a desktop application which is basically Google Local on steroids.
- Google Groups allows you to create a mailing list, read Usenet posts, and generally collaborate with others who share a similar interest.
- Google Homepage is a webpage which lets you add various widgets like weather, news, horoscopes and more, much like Netvibes.
- Google Image Search is Google’s slightly-lesser-known service to search for images.
- Google Labs highlights all the projects Google is working on for future release.
- Google Local combines data from Google Maps with information on local businesses and venues.
- Google Maps is a mapping service which also provides driving directions to and from different locations. The service is only available in a few countries (mainly the U.S.) but support for other countries is expected in the future. Google Maps has become quite popular lately thanks to a readily available API which lets people create their own maps.
- Google Mobile is similiar to Google SMS, but using WAP instead.
- Google Movie Showtimes lets you type in a zip code or address, and it will find movie theaters and showtimes near that area.
- Google News is a news portal, aggregated by Google’s computers. Everything is done by machines, so no human interaction.
- Google Reader is a new product which acts as a web-based RSS reader.
- Google Ridefinder lets you easily find taxis in some of the major cities around the United States.
- Google Scholar searches things such as theses, papers, and other research and technical information.
- Google Search History is technically part of the Google Homepage service, but does have its own page so it warrants a mention. Basically, if you sign in with a Google account, Google will keep track of all your searches done via its web search engine.
- Google Send to Phone is a little Firefox extension which lets you send text messages to mobile phones via SMS.
- Google Sitemap helps create particular searches for a web address which can be very useful for webmasters looking to index their own site, or see who is linking to it.
- Google SMS allows you to access many Google services through your mobile phone through text messaging (message GOOGL to learn more).
- Google Store isn’t really a service, but rather a place to buy some cool Google merchandise.
- Google Suggest is just an extension to the normal Google web search engine, but with autocomplete functionality to your searches making it a little easier to find what you need. There is also a Firefox extension available.
- Google Talk is Google’s IM and VoIP program running on the Jabber network. You need a Gmail account to use this.
- Google Toolbar is the swiss army knife of toolbars, if ever there was one letting your use the various Google web services from your toolbar, as well as offering other interesting information like a site’s PageRank and more.
- Google Language Tools lets you translate a phrase or entire website, as well as giving you access to web search in different languages, or the ability to search for a particular something in just one language.
- Google Video and Google Video Upload offer an archive of freely available video clips.
- Google Web Accelerator supposedly helps load web pages faster, but there have been security and privacy issues raised about this application.
- Google Web Search is the familiar web search. It also allows you to access certain functions like a calculator, a stock tracker, word definitions, travel information, weather, and more by simply searching for that information (for example, define onomatopoeia or weather 90210). These are not standalone services but a part of web search, which is why I’ve added them here and not into their own section. Additionally, there is the Advanced Search feature for…well…advanced searches which could be more precise than normal searches.
- Hello is a small IM client which is used in conjunction with Picasa to share pictures with family and friends.
- Orkut is a networking site similar to Frienster or MySpace, except it is invite only, so if you want to join it, you’ll have to know a guy, who knows a guy.
- Picasa is a fantastic digital photo organizer application for your desktop.
Now that you know about many of Google’s services, get out there and start Googling!
2006년 3월 13일 월요일
로드밸런싱과 NFS를 이용한 여러대의 서버를 사용하는 방법
|
2006년 3월 6일 월요일
2006년 2월 23일 목요일
SKTelecom - Telecommucations Review
- 매 짝수 달 25일에 발간하여 연간 총 6회 발행하며 특별부록을 1회 이상 발행할 수 있습니다.
- 호당 게재 논문 수는 15편 이하로 하며, 매 호당 약 5,000부를 발행하여 배포합니다.
- '논문집' 코너에서 PDF본을 제공하는 방식으로 Cyber출판도 병행합니다.
- 게재된 논문의 경우 편당 120만원의 연구지원비를 지급합니다.
Steve Friedl's Home Page
URL: http://www.unixwiz.net/Unixwiz.net - Software Consulting Central
Steve Friedl's Home Page
This is the website of Steve Friedl, a software and network security consultant in Southern California. You'll find a collection of tools, tech tips, and other information in the scope of my consulting practice. I've been a C and UNIX developer since 1981 and have an exceptionally broad background in this area. Some areas of expertise include:
- C and C++ systems software development on the UNIX and Win32 platforms
- Communications, including serial and TCP/IP based controllers
- Enterprise internet security administration and configuration
- Penetration tests, audits, and network reviews
- Security forensics, reverse engineering, and tools development
- General UNIX and Windows system/network administration
- The Windows Printing System
- Database software development
- Technology problem solving and research
- Technical writing and standup training
2006년 2월 22일 수요일
[아이뉴스24] 한국MS, 개인정보 보안강화용 윈도XP 공유컴퓨터 툴킷 발표
| 한국마이크로소프트(사장 유재성)가 공용 컴퓨터를 효과적으로 관리하고 개인정보 유출을 방지할 수 있는 윈도XP 공유 컴퓨터 툴킷 을 20일 발표했다. 웹사이트를 통해 무료로 내려받을 수 있는 윈도XP 공유 컴퓨터 툴킷 은 학교, PC방 등에 설치돼 있는 공용 컴퓨터에서 불특정 사용자가 변경해 놓은 제어판 설정, 원하지 않는 응용프로그램의 임의 설치, 사용자가 인지하지 못한 개인정보 유출 등을 방지할 수 있는 프로그램이라고 한국MS는 설명했다. 한국MS는 "이번 프로그램은 공용 컴퓨터의 하드 디스크를 무단 변경하지 못하게 하는 방어 기능과 허가되지 않은 사용자가 시스템 설정과 데이터에 접근하지 못하도록 하는 제한 기능을 지니고 있다"며 "사용자에게 보다 친근한 인터페이스를 구성할 수 있는 향상 기능을 통해서는 접속 때마다 사용자 설정과 데이터를 새로 고쳐 개인정보를 보호할 수 있다"고 지적했다. 박준석 한국MS 윈도 클라이언트운영체제 마케팅 담당 부장은 "이번 프로그램은 누구나 쉽게 무료로 내려받을 수 있어 별도 PC 관리자가 없는 학교, 도서관, PC방 등에서 효과적으로 사용할 수 있을 것으로 보인다"며 "최근 공용 컴퓨터를 통한 개인정보 유출 문제가 심각해지고 있어 이러한 문제를 방지하는 데 큰 기여를 할 것"이라고 강조했다. 윈도우XP 공유 컴퓨터 툴킷 에 대한 자세한 내용은 전용 웹 사이트(http://www.microsoft.com/korea/windowsxp/sharedaccess/default.mspx)에서 확인할 수 있다. /이정호기자 sunrise@inews24.com 출처: 아이뉴스24, 2/20/2006, 2:12:29pm, http://news.inews24.com/php/news_view.php?g_serial=192376&g_menu=020200 |
2006년 2월 20일 월요일
PCBstandards.com
Excellent site for SMT, PCB, electronic design information, and useful Excel spreadsheets for EE related formulas. Hit the "SITE MAP" button for a list of all the documents.
SMTinfo.net HomePage
A very good site for general SMT design guidelines as well as plenty of useful links
Board level assembly and reliability considerations for QFN type packages
Amkor Technology, Inc.
1900 S. Price Road
Chandler, Arizona
ABSTRACT
There is a strong interest in understanding the surface mount assembly requirements of QFN (Quad Flat No-Lead) type packages due to their rapid industry acceptance. Board level reliability is also of great concern as this is a package without compliant leads. This paper provides guidelines in board design and surface mount of this package based on extensive surface mount experiments. Board level reliability data has also been generated for accelerated temperature cycling test conditions and is presented here. The data is generated for different material sets, various body/die sizes, temperature cycle conditions and board thickness. The data shows reliable surface mount process is achievable and the package is very reliable for most applications.
Source: http://www.amkor.com/products/notes_papers/Board_Level_QFN.pdf
2006년 2월 1일 수요일
[S/W] ID 혹은 이메일 주소 일부를 **로 처리하기
필요하신 분들 꼭 한번 써 보세요.
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가끔 워드나 엑셀 작업을 하면서 아이디의 일부를 ** 처리할 경우가 있다.
그 방법을 소개한다. 본인이 잘 까먹어서 노하우에 올린다. ^^
- 엑셀 파일에서 아이디를 정렬한다.
- 일부를 ** 처리하고 싶어하는 아이디의 다음 열에 @naver.com과 같이 구분할 수 있는 인자를 붙여준다. 한칸 띄고 입력한다.
- 아이디와 @naver.com 두 열을 카피해 메모장에 붙인다.
- 메모장에서 다시 카피해 워드에 붙인다.
- 워드의 바꾸기 기능을 이용해 바꾼다. 함수는 아래와 같다.
찾기 : ^?^?^t @naver.com
바꾸기 : **^t @naver.com
이렇게 하면, @ 앞에 있는 임의의 문자 2개가 **로 변환된다.
각주 1) ^? 의 의미 : 임의의 문자를 지칭, ^t 의 의미 : 탭을 의미
즉, 임의의 문자 2개는 @와 한탭을 사이에 두고 있는 것으로, @ 앞에 한 탭 띄고 있는 임의의 문자 두개를 **로 바꾼다는 함수이다. - 워드에서 변환된 값을 카피해 엑셀에 붙인다.