 | 은하철도 999 TV시리즈 1 & 2 & 3 한정판(59DISC) -  니시자와 노부타카 외 감독/미라지엔터테인먼트 |
- 이걸 사~? 말어~? 어쩐다...^^;;;
2010년 6월 28일 월요일
은하철도 999 TV시리즈 1 & 2 & 3 한정판(59DISC)
- 이걸 사~? 말어~? 어쩐다...^^;;;
2010년 5월 26일 수요일
액텔, 하드형 ARM 코어 통합한 플래시 기반 FPGA 선보여
EDA/IC 설계
액텔, 하드형 ARM 코어 통합한 플래시 기반 FPGA 선보여
게재:2010년05월14일
Dylan McGrath
EE Times
Actel사가 임베디드 디자이너들의 폭 넓은 관심을 끌만한 중요한 발전이라고 밝힌 플래시 기반 FPGA(field programmable gate array) 제품군을 출시했다. 이 FPGA 패브릭은 하드형(hard) ARM Cortex-M3 프로세서로 구축된 완벽한 마이크로컨트롤러 서브시스템 및 프로그램 가능형 아날로그 블록과 통합되어 있다. SmartFusion 제품군의 첫번째 제품은 대량 생산 중으로 현재 이용 가능하다.
Actel사에 따르면, 디자이너들은 SmartFusion 디바이스를 통해 보드 레벨을 변경하지 않고도 하드웨어/소프트웨어 트레이드오프를 즉시 최적화시킬 수 있다고 한다. 프로세서와 필수 글루 로직을 한 디바이스에 제공함으로써 성능과 비용 및 풋프린트의 이점을 제공한다고 Actel사의 경영진들은 밝혔다.
“SmartFusion은 CPU 코어만이 아니라 완전한 마이크로컨트롤러 서브시스템을 갖추고 있다”고 Actel사의 세일즈 및 마케팅 VP인 Rich Kapusta 씨는 말했다. “최초로 성능에 대한 타협 없이 FPGA 및 마이크로컨트롤러를 일부 프로그램 가능형 아날로그와 통합했다.”
컨설팅 업체인 Silicon Insider사의 사장인 Jim Turley 씨에 따르면, 디자이너들은 약 10년 동안 프로세서들을 FPGA에 통합시키기 위해 노력해 왔지만 프로그램 가능형 패브릭과 프로세서 아키텍처가 조화되지 못하고 이 구성요소들 간의 통신이 느려짐으로써 그다지 큰 성공을 이루지 못했다고 한다. “Actel사는 SmartFusion을 통해 일반적인 ARM 프로세서와 FPGA 패브릭을 결합시켰을 뿐만 아니라 이 둘을 원활하게 통신할 수 있는 방식으로 통합시켰다”고 Turley 씨는 말했다.
SmartFusion은 2005년에 시장을 강타한 Actel사의 첫번째 혼성신호 FPGA인 Fusion에서 발전된 제품이다. Fusion 디바이스는 32비트 ARM Cortex-M1 등의 소프트 프로세서 코어를 통합할 수 있다.
Actel사의 마케팅 및 엔지니어링 수석 VP인 Fares Mubarak 씨는 Fusion이 시장에서 성공을 거두긴 했지만 Actel사는 타깃 어플리케이션의 폭을 보다 넓히고 싶어했다고 밝혔다. 이를 위해 Actel사는 프로세서를 강화하고 표준 주변기기에 대한 전체적인 보완 요소를 제공함으로써 프로세서 이외의 성능도 높여야만 했다.
“Actel사는 플래시 공정에 상당한 투자를 했기 때문에 이 새로운 제품군이 누구도 쉽게 복제할 수 없는 지속 가능하며 차별화된 디바이스라는 점에 대해 상당히 만족해 했다”고 Kapusta 씨는 말했다.
SmartFusion은 내장 플래시 메모리를 갖춘 CortexM3를 제공하는 한편, SRAM 기반 FPGA는 외장 플래시를 필요로 한다고 Kapusta 씨는 덧붙였다. 또한 그는 이러한 플래시 기술을 통해 SmartFusion에서 고전압 아날로그가 디지털 회로와 공존할 수 있는 것이라고 설명했다.
Actel사는 SmartFusion이 FPGA, 프로그램 가능형 아날로그 및 마이크로컨트롤러가 교차하는 광범위한 시장의 흥미를 끌 수 있을 것으로 생각하고 있다. SmartFusion은 산업, 군사, 의료, 통신, 컴퓨팅 및 스토리지 시장의 시스템 및 전력 관리, 모터 제어, 산업 자동화, 디스플레이와 같은 다양한 어플리케이션들을 타깃으로 하고 있다.
그러나 Actel사의 경영진들은 SmartFusion이 학습 곡선이 필요할 수도 있다면서, 특히 FPGA는 익숙하지만 마이크로컨트롤러에 대해서는 생소하다거나 그 반대의 상황인 디자이너들의 경우 그러할 것이라고 인정했다.
따라서 Actel사는 이 디바이스를 위한 설계 지원을 위해 Libero IDE(Integrated Design Environment)를 제공하며 GNU를 갖춘 무료 SoftConsole Eclipse 기반 IDE뿐만 아니라 Keil 및 IAR Systems사의 평가 소프트웨어 버전을 제공한다.
Actel사에 따르면, SmartFusion 디바이스에 통합된 마이크로컨트롤러 서브시스템은 ARM Cortex-M3 기반으로 100MHz 동작 속도를 가진다고 한다. 또한 최대 512킬로바이트의 플래시 메모리와 64킬로바이트의 SRAM 등이 포함되어 있다.
SmartFusion 디바이스는 Actel사의 플래시 기반 ProASIC3 FPGA 아키텍처로 제작되고 130나노 CMOS 공정에서 구현되며 6만~50만 개의 시스템 게이트와 350MHz의 성능으로 최대 204개의 입출력을 지원한다.
Actel사는 지난해 9월 이후부터 SmartFusion 디바이스를 샘플링해 왔으며 수십 곳의 고객사들과 협력을 진행해 왔다고 밝혔다. SmartFusion 제품군의 첫번째 제품인 A2F200은 대량 생산 중으로 현재 이용 가능하다. 또한 A2F500 디바이스들은 올해 2분기에 공급될 예정이며 A2F060 디바이스들은 올해 하반기에 공급될 전망이다.
고객 평가를 위한 샘플 개발 킷은 99달러에 제공되고 모든 기능을 갖춘 개발 킷은 999달러에 공급되며 두 개발 킷 모두 현재 바로 사용할 수 있다고 Actel사는 밝혔다.
본 기사는 http://www.eetkorea.com/ART_8800606711_480103_NP_dc456e9e.HTM에 있는 전자 엔지니어 기사에서 인쇄한 것입니다.
ADC 구현 위한 FPGA 및 CPLD 디지털 로직 강화
증폭, 컨디셔닝 및 변환
ADC 구현 위한 FPGA 및 CPLD 디지털 로직 강화
게재:2010년05월03일
By Ted Marena
Lattice Semiconductor Corp.
디지털 시스템 설계자들은 다양한 프로세서, 메모리 및 표준 함수 컴포넌트들을 인쇄회로기판에 모두 포함시키기 위해 FPGA와 CPLD를 이용해 디지털 설계의 ‘나머지 부문’을 구현하는 데 익숙하다. 이러한 디지털 함수 외에도 FPGA와 CPLD는 LVDS 입력과 간단한 저항 커패시터(RC) 회로 및 FPGA나 CPLD 디지털 논리 소자 일부를 이용하는 공통 아날로그 함수를 구현함으로써 ADC를 제작할 수 있다.
ADC는 보편적인 아날로그 빌딩 블록으로서, FPGA나 CPLD와 같이 디지털 로직을 ‘현실 세계’의 아날로그 센서로 인터페이싱할 때 거의 항상 필요하다. 여기에서는 Lattice Semiconductor사의 유용한 레퍼런스 디자인과 데모 보드를 이용해 저주파수(DC~1KHz)와 고주파수(최대 50KHz) ADC 두 가지를 모두 구현하는 것에 대해 설명할 것이다.
네트워크 스위치 내 시스템 모니터를 위한 어플리케이션과 오디오 통신 시스템 내 주파수 감지를 위한 어플리케이션 등 각 디자인을 위한 간단한 어플리케이션이 검토될 것이다.
ADC 구현의 개요
간단한 ADC는 소형 RC 회로를 FPGA나 CPLD의 LVDS 입력에 추가함으로써 이루어질 수 있다. 그림 1의 좌측 하단에 나타나 있는 바와 같이 RC 네트워크는 LVDS 입력의 한쪽 측면에 위치해 있으며 아날로그 입력은 다른 한 쪽에 자리잡고 있다.
LVDS 입력은 간단한 아날로그 비교기 역할을 하게 되며 아날로그 입력 전압이 RC 네트워크의 전압보다 높은 경우 디지털 ‘1’을 출력하게 된다. LVDS 비교기는 입력 쪽의 전압을 RC 회로로 변화시킴으로써 정확한 디지털 표시를 구현하기 위한 아날로그 입력 전압 분석에 이용될 수 있다.
아날로그-디지털 제어 모듈은 아날로그 입력 주파수, 목표 분해능 및 이용 가능한 로직 리소스에 따라 다양한 방법으로 구현될 수 있다. 그림 1의 좌측 상단 옵션 1에서 볼 수 있듯이 저주파수 신호는 간단한 연속 근사 레지스터를 이용해 처리될 수 있다.
그림 1: ADC(analog to digital converter)의 기본 블록 다이어그램: 저주파수 및 고주파수 옵션
그림 1의 우측 상단에서 볼 수 있듯이 보다 높은 주파수의 구현은 샘플링 레지스터와 CIC(cascade integrated comb) 필터를 구성하는 델타 시그마 변조 함수를 이용해 이루어질 수 있다.
디지털 신호가 구성되면 디지털 출력이 수시로 필터링됨으로써 시스템 잡음이나 피드백 지터로 인한 원치 않는 모든 고주파수 컴포넌트를 제거할 수 있다.
디지털 필터 블록 옵션에 이어서 메모리 버퍼 옵션이 디버깅/테스팅 목적으로 이용될 수 있다. 디지털 출력은 메모리 버퍼에 의해 샘플링되고 그 후 신호 분석 소프트웨어가 구동되고 있는 PC의 JTAG 포트를 통해 스캔 아웃된다.
저주파수 로직 ADC 구현 설명
저주파수 로직 구현에서 샘플링 제어 모듈은 연속 근사 레지스터를 제어하며 일반 출력 신호가 RC 회로에 적용되는 시간을 변경시킨다. 따라서 RC 회로 전압은 일반 출력의 상태, 즉 변화된 값에 따라 증가되거나 감소한다.
LVDS 입력은 변화하는 RC 회로 전압을 아날로그 입력과 비교한다. 그 결과 RC 회로 전압은 아날로그 입력 전압을 ‘찾는 데’ 이용된다. 그림 2는 전체 입력 전압 범위의 반값에 약간 못 미치는 정적 아날로그 입력(오렌지색 점선)의 실례를 보여 준다. 흑색 수직 점선은 녹색 점선으로 표시된 SAR 샘플 지점 사이의 클럭 수를 나타낸다.
첫번째 계측은 8클럭이 걸리며 다음은 4클럭, 2클럭 등이 걸리게 된다. 처음에 RC 회로는 로직 ‘1’이 일반 출력에 적용됨으로써 아날로그 입력에서 전체 전압 진폭의 반값까지 상승하게 된다. 전압이 2분의 1 지점에 오게 되면 LVDS 입력에 대한 출력은 아날로그 입력값이 RC 회로 전압 이상인지 이하인지를 나타내게 될 것이다.
아날로그 전압이 더 높으면 디지털 출력에서 가장 중요한 비트가 로직 ‘1’이 된다. 아날로그 전압이 더 낮으면 디지털 출력은 로직 ‘0’이 된다. SAR은 반으로 줄어드는 샘플링 시간을 따라 다음 비트로 이동한다. 이러한 과정이 ADC의 정확도가 목표에 도달할 때까지 반복된다.
그림 2: SAR(Successive Approximation Register) 기반 ADC 동작 실례
그림 2의 예를 통해 RC 회로 전압이 어떻게 아날로그 입력값에 단계적으로 도달하는지를 관찰할 수 있다. 이 다이어그램의 하단에는 SAR(0101)의 4비트 디지털 출력이 나타나 있다.
저주파수 디자인은 다양한 공급 전압 및 환경 센서에 해당하는 몇 가지 아날로그 전압 레벨을 모니터링 하는 데 이용될 수 있다. CPLD 구현은 PCB 전원 공급 전압(3.3V, 2.5V 및 1.8V)뿐만 아니라 온도/습도 센서 및 오픈 캐비닛 알람을 모니터링 할 수 있다.
다수의 아날로그 입력을 계측하기 위해 하나의 LVDS 입력이 추가 RC 회로와 함께 각각의 아날로그 전압에 이용된다. 아날로그 전압은 천천히 변화되기 때문에 LVDS 출력이 다중화됨으로써 디지털 로직 함수가 각각의 입력 사이에 공유될 수 있다.
저주파수 로직 ADC 테스트 결과
Lattice MachXO CPLD에는 개발 보드를 이용해 디지털 필터 옵션이 없는 저주파수/최소 로직 회로가 구현되었으며 0~3.3V의 진폭에 0.8Hz의 입력 신호가 이용되었다.
그림 1에서 볼 수 있는 메모리 버퍼 옵션은 Lattice ispLever 디자인 소프트웨어의 Lattice Reveal Logic Analyzer 기능과 함께 이용된다. 이 기능은 디지털 신호 캡처, 데이터 버퍼링 및 JTAG 케이블을 통해 컴퓨터로 데이터를 전송하는 작업을 제어하는 데 필요한 로직 이외의 타깃 디자인에 버퍼 메모리를 추가시켜 준다. 테스트가 진행되는 동안 FFT는 Linear Technology사의 Pscope 소프트웨어를 이용해 수집된 데이터를 기반으로 구동된다.
수신된 디지털 신호는 Pscope 스크린 캡처 창의 상단에 표시된다. 세로축은 코드 스텝으로 측정하며(0~255) 가로축은 샘플로 측정한다(여기서는 1024샘플). 주파수는 f1(기본) 주파수와 같이 우측 상단의 박스에 기록된다. FFT의 결과는 창의 하단에 표시되며 고주파 주파수는 dB 레벨에 따라 세로축으로 표시된다.
FFT에서 발생한 핵심 파라미터들에 대한 요약 내용은 우측 하단 박스에 표시되며 여기에는 ENOB(effective number of bits)와 SNR(signal to noise ratio)도 들어 있다. 이 결과들은 입력 신호가 우수한 분해능과 SNR로 디지털 신호로 성공적으로 변환되었음을 나타내 준다.
고주파수 ADC 구현
그림 1의 우측 상단에 있는 고주파수 ADC 옵션의 프론트엔드는 여전히 RC 회로와 LVDS 입력을 이용하고 있다. 오버샘플링 플립플롭은 LVDS 입력으로부터 비교기 결과를 캡처한다. 이 신호는 RC 회로를 구동시키는 일반 LVCMOS 출력을 통해 피드백된다. 비교기 출력이 로직 ‘1’이라면, 이는 아날로그 입력이 RC 회로의 전압보다 높다는 것을 의미한다.
로직 ‘1’이 플립플롭에 의해 샘플링되고 RC 회로로 피드백됨으로써 RC 회로 전압은 상승하게 된다. 비교기의 출력이 로직 ‘0’이면 피드백 신호는 로직 ‘0’이 되며 RC 전압은 보다 낮아지게 된다. 이 간단한 피드백 메커니즘을 통해 디지털 값은 아날로그 입력 주파수를 ‘트래킹’하는 것이다.
그림 3: 델타시그마 모듈레이터의 변환 스테이지 결과를 보여준다.
그림 3의 우측 하단 그래프의 적색선은 샘플 아날로그 입력 파형과 샘플링 플립플롭의 출력을 나타내며 청색 칸은 로직 ‘1’을 나타내고 백색 칸은 로직 ‘0’을 나타낸다. ‘1’과 ‘0’이 공통 PCM(pulse code modulated) 포맷으로 변화되는 방식을 살펴 보자.
PCM 입력은 CIC(cascaded integrator comb) 필터를 이용해 아날로그 입력 스트림 주파수를 반영하는 출력 스트림으로 변환될 수 있다. CIC 기능은 근본적으로 단일 비트 PCM 신호를 통합하고 있어서 원하는 비트 수로 지속적인 출력 신호를 발생시킨다.
그림 3의 하단부의 예에서 청색 비트는 ‘1’로 백색 비트는 ‘-1’로 간주되는데 합계(통합) 작업이 입력 파형에 대한 디지털 표현을 발생시키는 것이 확실하다.
RC 회로의 전압은 이 피드백 루프를 통해 구현된 “트래킹” 과정으로 인해 아날로그 입력 레벨 주변에서 왔다 갔다 하게 된다. RC 회로 전압은 오버샘플링 플립플롭이 ‘1’과 ‘0’이라는 결과 사이에서 변화되는 것과 같이 아날로그 입력 레벨보다 약간 높거나 낮은 범위 안에서 변하게 된다. 이러한 고주파수 잡음은 부수적인 디지털 필터를 이용함으로써 제거할 수 있다.
고주파수 설계는 동작 및 환경 상태를 전달하는 데 이용되는 다중 오디오 주파수 보조 신호를 모니터링 할 수 있다. 예컨대, 5kHz 및 12kHz 신호가 주기적으로 발생됨으로써 원격 오디오 모니터링 시스템의 상태를 표시할 수 있다. 이러한 신호들은 장비의 환경 상태(온도 및 습도)를 나타낼 수 있다.
앞선 예에서와 같이 다중 아날로그 신호들은 간단하게 보다 많은 LVDS 입력을 추가함으로써 지원될 수 있다. 이 디자인은 최대 8개의 아날로그 신호를 위한 허브가 될 수 있다.
고주파수 ADC 테스트 결과
보다 높은 주파수의 ADC 회로가 개발 보드를 이용해 Lattice XP2-17 FPGA에 구현되었다. 0~3.3V 진폭의 15kHz 입력 신호가 테스트 동안 이용되었다. 이 아날로그 신호는 디지털 필터 옵션을 이용하는 그림 1에 보이는 옵션 2 회로를 이용해 처리된다.
결과가 표시된 창을 보게 되면, 수신된 신호는 상단 창에 표시되고 FFT는 하단에 표시되며 가장 중요한 f1 주파수는 15.1kHz로 표시되는 것을 볼 수 있다. 측면 박스에는 ENOB은 9비트이며 SNR은 61dB라는 결과가 기록된다. 이러한 결과들은 입력 신호가 디지털 신호로 우수한 분해능과 SNR을 통해 성공적으로 변환되었음을 나타내 준다.
<이번호 저널 2010년 5월>호에서 이 기사 및 다른 기사들도 찾아볼 수 있습니다.
본 기사는 http://www.eetkorea.com/ART_8800605154_839591_NT_52a2da9b.HTM에 있는 전자 엔지니어 기사에서 인쇄한 것입니다.
2010년 5월 24일 월요일
2010년 5월 2일 일요일
Xilinx revisits the embedded-CPU FPGA
Wednesday, April 28, 2010
Nearly a decade ago Xilinx and Altera set a new direction for the FPGA industry, each announcing a high-end FPGA sitting beside a powerful CPUs on one die. Enticed by what had been explosive growth in a networking industry that was in fact using MPUs and high-end FPGAs side by side on their boards, the programmable-logic leaders poured development and marketing dollars into their new flagship ICs, Altera Excalibur and Xilinx Virtex-II Pro.
If this story doesn't sound familiar, it's because the two chips were both doomed to vanish. Within about a year both chips were no longer actively marketed, though you could still buy them. Quiet settled over the scene of the revolution, dust gathered on the engineering notebooks, and both companies silently pledged not to try that again.
Exactly what went wrong is a difficult question. There is always enough blame to go around when an entire product category fails. Certainly the issue was not silicon execution: both the chips were heavily used in the academic community, as the platforms for research that became much of the foundation of today's heterogeneous multicore embedded computing.
Rather, the issues were more practical. By the time they were shipping, Excalibur and Virtex-II Pro were comparatively expensive ways to buy what had become a mature microprocessor. So the significant added cost of the FPGA-based parts was hard to justify for production. There was also the problem of configuration. As any product manager can attest, anything you integrate into a chip is the wrong choice for the next customer you talk to. You have the wrong CPU, or the wrong memory architecture, or not the right peripherals, or not enough or too much FPGA fabric. Finally, and perhaps the most serious problem for both chips, the interface between the CPU and FPGA sides of the die is always problematic. An interface powerful and flexible enough for experienced SoC architects is incomprehensible to traditional FPGA users.
All this notwithstanding, yesterday ARM and Xilinx announced another cut at the challenge: the Extensible Programming Platform (or EPP, if you will allow.) With perhaps a nervous glance over the shoulder to check for the spectre of Virtex-II Pro, the company is positioning this product not as an FPGA with an on-chip CPU, but as a software execution platform that happens to facilitate configurable hardware accelerators and peripherals. The difference may sound like words, but it is more than marketing-program deep.
The EPP is architected somewhat differently from the earlier chips. Like them, it is divided into a processor portion and an FPGA portion. But the EPP's processor side is nearly self-contained, comprising a pair of ARM Cortex-A9MP CPU cores, along with the NEON media engine, the debug core, the recently-released AXI-4 interconnect IP, caches, DRAM controller, and typical peripherals. Xilinx senior vice president of marketing Vincent Ratford pointed out that the CPU side of the chip is sufficiently autonomous that it can boot Linux before the programmable fabric is even configured. The FPGA side will apparently look a lot like a moderate-sized Virtex-6, with fabric, block RAM, probably DSP blocks, and, in some versions, fast SerDes.
The interconnect between the two sides is a more interesting subject. Ratford said that about 2500 signals will cross the boundary between the CPU and FPGA regions. That apparently includes both the high-bandwidth main bus and the peripheral bus of the AXI network. It is not clear just how the multi-layer nature of AXI will be propagated into the FPGA fabric. ARM's multicore coherency bus also will extend into the fabric, according to ARM Physical IP Division executive vice president and general manager Simon Segars. So it should be possible for sophisticated users to implement coherent caches and local memories for accelerators in the FPGA Block RAM.
The chip will use TSMC's 28HPL process, and Xilinx plans to sample at least one version sometime in 2011—a pretty big window. Ratford said there would be several versions of the die with different processor subsystems.
The user design flow will be quite different from the traditional FPGA flow. Ratford said "This product targets the software developers." The concept is that developers—presumably starting with a reference design—would use ARM's RealView Development System to bring up an application in C/C++. Then they would profile the code execution, identify hot spots and critical sequences, and call in the hardware team with behavioral synthesis tools to massage the underperforming C into RTL. From there, the RTL would go into Xilinx's ISE 12 tool chain, eventually becoming a configuration file for the FPGA side of the chip. There are plans to link RVDS and ISE at some critical points to allow debug in both environments at once. Xilinx is also exploring Matlab and Labview as design-origination tools.
So are there enough fundamental differences to predict a better fate for the EPP than overtook the Virtex-II Pro? Some things are indeed profoundly different this time. First, you can put vastly more hardware into a large 28nm die than you could into a big chip ten years ago. That means more performance, a please-almost-everyone selection of peripherals at a decent cost point, room for more capable accelerators, and—desperately important—much more on-chip memory. Second, the ARM architecture is far more ubiquitous today than the PowerPC was then. So even if the big networking vendors are once again unimpressed, many other applications are still available. These two facts should substantially reduce barriers to market acceptance of the new architecture.
Third, EPP will probably be one of the first implementations of Cortex-A9 in 28nm to be available to the general market, not a late-coming and expensive alternative to a two-chip approach. Even though the A9 has been announced for about a year now, many users may find the EPP a very accessible way to get at one. If users see value in the FPGA portion of the die as well, the EPP could look like a good deal. And finally, the EPP is addressed to a very different market than Virtex-II Pro. The earlier chip was aimed at FPGA experts. EPP is addressed to software-dominated design teams in which hardware engineers play a supporting role.
Will it work? There remain two major questions. First, can the kind of software-first methodology Xilinx envisions successfully produce a working SoC with today's tools, or will the design require early engagement by FPGA experts, careful system modeling and parallel hardware and software development? If the latter is the case, much of the advantage of the EPP is lost. Second, can Xilinx hide from designers the complexity of the interface between the CPU and FPGA sides of the die, without obscuring the power of the architecture? Neither software developers nor traditional FPGA users are going to cope successfully with the interface in all its riches. Yet the advantage of the EPP over a commodity microprocessor used with an inexpensive FPGA rests in users' ability to exploit that interface. Only time can answer these two questions.
© Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
==========
추천: http://www.edn.com/blog/1690000169/post/110054211.html?rid=#EDNRegVisitorID#&nid=2435
2010년 4월 29일 목요일
Parallel Engines Launches World’s Largest Semiconductor-IP Directory for FPGA
|
Xilinx Unveils ARM-Based Processing Architecture for Delivering Unrivaled Levels of Performance in Embedded Systems
press release
April 27, 2010, 5:00 p.m. EDT
Xilinx takes processor-centric approach to deliver platform that combines the best of serial and parallel processing
SAN JOSE, Calif., April 27, 2010 /PRNewswire via COMTEX/ -- Embedded Systems Conference -- Xilinx Inc. /quotes/comstock/15*!xlnx/quotes/nls/xlnx (XLNX 26.54, +0.24, +0.91%) today introduced the architecture for a new Extensible Processing Platform that will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM(R) Cortex(TM)-A9 MPCore(TM) processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenging system requirements presented by the global demand for embedded systems to perform increasingly complex functions.
The Xilinx(R) Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing -- or any combination thereof -- needed to meet their application-specific requirements, including lower cost and power.
"Today's embedded software developer is being tasked to build complex applications that require tremendous levels of system performance, and they need to deliver that performance within tightly managed cost, schedule and power budgets," said Vin Ratford, Xilinx Senior Vice President for Worldwide Marketing and Business Development. "By creating an architecture within a familiar ARM processor-based development framework, this new Extensible Processing Platform can be the engine of innovation for many design teams held back today by performance bottlenecks."
A software-centric development flow is enabled by a processor-centric approach which presents a full processor system - including caches, memory controllers and commonly used connectivity and I/O peripherals - that boots and can run a variety of operating systems (OS) at power-up, such as Linux, Wind River's VxWorks and Micrium's uC-OSII. The ARM architecture and its Connected Community ecosystem further maximize productivity for developers of embedded systems, while unrivaled performance is achieved by Xilinx's architecting the subsystem around ARM's dual-core Cortex(TM)-A9 MPCore(TM) processors, each running at up to 800 MHz, combined with the parallel-processing capabilities of Xilinx's high-performance, low-power 28-nanometer programmable logic. The programmable logic is tightly coupled with the processor system through the high-bandwidth AMBA(R)-AXI(TM) interconnects to accelerate key system functions by up to 100x, using off-the-shelf and/or custom IP. This architectural approach addresses common performance bottlenecks between these parallel and serial computing environments, memory and I/O. It also gives the processor system configuration control of the programmable logic, including dynamic reconfiguration.
"Taking advantage of the parallelism of programmable logic is an excellent method for overcoming cost and power challenges in systems that require significant levels of high performance," said Simon Segars, President ARM Inc. "Xilinx's new architecture abstracts much of the hardware burden away from the embedded software developers' point of view, giving them an unprecedented level of control in the development process."
Software developers can leverage their existing system code based on ARM technology and utilize vast off-the-shelf open-source and commercially available software component libraries. Because the system boots an OS at reset, software development can get under way quickly within familiar development and debug environments using tools such as ARM's RealView development suite and related third-party tools, Eclipse-based IDEs, GNU, the Xilinx Software Development Kit and others.
Unrivaled Performance to Enable New Applications
Demand for higher levels of embedded system performance is being driven by end market applications that require multifunctionality and real-time responsiveness, such as automotive driver assistance, intelligent video surveillance, industrial automation, aerospace and defense, and next-generation wireless. In the automotive sector alone, with greater than 50 million cars produced each year, and an estimated 600 million motor vehicles on the road, today's $1.3-billion-dollar driver assistance market is expected to grow to $5.8 billion by in 2017(1) as manufacturers deploy more embedded systems in their vehicles to make them safer.
With statistics showing that 60 percent of front-end collisions could have been avoided with an extra .5-second response time, or that driver fatigue accounts for an estimated 30 percent of all driver fatalities, the motivation to leverage technology to save lives is clear. As developers of driver assistance systems pack more compute power into their applications, radar and infrared sensors, cameras and other system components must be installed into confined spaces within the automobile. The new Xilinx Extensible Processing Platform offers a single-chip solution for optimizing application-specific hardware/software partitioning and accelerating functions in hardware to drive complex algorithms. This enables customers to further differentiate their embedded systems to gain a competitive advantage in their markets.
In a market expected to reach $46 billion by 2013(2), developers of new intelligent video technologies need processing platforms for building applications that can automatically monitor video patterns and body language, combined with audio, to make intelligent decisions and send alerts, thus reducing the chance for errors. The technology is already moving to full high-definition video and frame rates up to 60 frames per second, but current solutions do not offer sufficient compute power for image processing and advanced analytic functions. The dual Cortex-A9MPCore-based processor system, coupled with the massive parallel-processing capabilities of the programmable logic, enables this capability. Developers also gain an opportunity for innovative algorithm design, scalability and field upgradability within a familiar ARM-based design environment.
Wireless telecommunication is being driven by the need for lower power, smaller physical form factors and reduced development costs, to support an ever-increasing number of users and data-hungry applications. New technologies such as 4G LTE (Long-Term Evolution) can address bandwidth requirements, but smaller, more efficient base stations are essential to meeting overall market requirements. The Xilinx Extensible Processing Platform will help developers of next-generation wireless base stations to meet these needs by providing high-bandwidth parallel processing of 4G signals in combination with multiuser data management on Cortex A9 processors - all in a small, power-efficient, cost-effective integrated solution. Because the platform is extensible, developers have the flexibility to implement future equipment updates and performance upgrades of both hardware and software.
The new Extensible Processing Platform is part of Xilinx's Targeted Design Platform strategy, which provides customers with market- and application-specific environments that are easy to use, enabling them to evaluate and understand technology, and finally provide application platforms that can be modified and extended to accelerate their development time and focus on differentiation. Xilinx has also engaged with ARM Services to provide detailed ARM Cortex-A9 hardware training for design teams and field application engineers who will be supporting the eventual product rollout.
Visit the Xilinx booth (#1716) at the Embedded Systems Conference to see and learn more. Pricing and availability will be announced for products based on the Extensible Processing Platform architecture in early 2011. Visit www.xilinx.com/technology/roadmaps and click the link to "Be the First to Know" for product details, as they become available.
About Xilinx
Xilinx is the world's leading provider of programmable platforms, with more than 50 percent market share in the programmable-logic device (PLD) segment of the semiconductor industry. For more information, visit www.xilinx.com.
#1023P
XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
(1) Intelligent Car Initiative- Europe's Information Society; International Organization of Motor Vehicle Manufacturers; http://www.worldometers.info/cars/
(2) Multi-media Intelligence Report - April 2008
Editorial Contact:
------------------
Bruce Fienberg
Xilinx, Inc.
408-879-4631
bruce.fienberg@xilinx.com
SOURCE Xilinx, Inc.
Copyright (C) 2010 PR Newswire. All rights reserved.
==========
Xilinx hardwires Cortex-A9 MPCore processor into FPGA
Richard Wilson
Tuesday 27 April 2010 22:01
Xilinx has introduced its first FPGA design platform with an embedded ARM Cortex-A9 MPCore processor.
Xilinx has worked with ARM for over a year to allow the programmable logic elements of the FPGA, with their highly parallel architecture, to be closely coupled with the processor system through the AMBA-AXI on-chip bus.
According to the FPGA supplier, this architectural approach “addresses common performance bottlenecks between these parallel and serial computing environments, memory and I/O.”
“It also gives the processor system configuration control of the programmable logic, including dynamic reconfiguration,” said Xilinx.
“By creating an architecture within a familiar ARM processor-based development framework, this new Extensible Processing Platform can be the engine of innovation for many design teams held back today by performance bottlenecks,” said Vin Ratford, Xilinx senior v-p for worldwide marketing and business development.
The processor subsystem is based around ARM’s dual-core Cortex-A9 MPCore processors, each running at up to 800MHz.
The aim has been to offer within the FPGA a full processor system including caches, memory controllers and commonly used connectivity and I/O peripherals.
Efforts have also been made to support different operating systems such as Linux, Wind River’s VxWorks and Micrium’s uC-OSII.
The aim is to allow developers to tap into off-the-shelf open-source and commercially available software component libraries.
“Because the system boots an OS at reset, software development can get under way quickly within familiar development and debug environments using tools such as ARM’s RealView development suite and related third-party tools, Eclipse-based IDEs, GNU, the Xilinx Software Development Kit and others,” said Xilinx.
The AMBA-AXI bus protocol has been redesigned to make it compatible with highly parallel embedded FPGA design. It adds support for longer bursts which will support devices with large block transfers.
There is also quality of service (QoS) signalling to manage latency and bandwidth in complex multi-master systems.
“This will take embedded system design to performance and efficiency levels considered the exclusive domain of desktop, laptop and network equipment,” said Keith Clarke, v-p and general manager of fabric IP processor division at ARM.
The first FPGAs based on what the company is calling the Extensible Processing Platform will be available next year.
See: Xilinx brings ARM Cortex and AMBA to its FPGAs
==========
NEWS ANALYSIS - Xilinx puts ARM core into its FPGAs
New embedded systems architecture employs ARM core in processor-centric FPGAs.
By Richard Nass
(04/27/10, 05:00:00 PM EDT)
My first reaction was, "It's about time." My second reaction was, "I hope they did it right." Let me explain. Xilinx, considered by many to be the market leader for FPGAs, had a hole in its lineup, at least in my eyes. For at least a couple of years, I asked the folks at Xilinx why they weren't making a serious run at ARM-based FPGAs.
I learned that it wasn't as simple as dropping the core into the company's library. There were It actually took some design issues that needed to be overcome to ensure that the ARM core could operate at its maximum efficiency. Those changes were put in place last fall, when Xilinx announced a technology agreement with ARM.
Essentially, the technology agreement revolved around changes made to the AMBA bus to keep the programmable logic tightly coupled with the processor core. Xilinx adopted ARM physical IP, and the two companies made a technical commitment to work together to define the AMBA 4 specification, which is the de-facto industry standard for on-chip communications on SoCs designed with an ARM core.
With that technology in place, it was clear where Xilinx was headed. However, there were a few details on which Xilinx remained mum. As of today at the Embedded Systems Conference Silicon Valley, that silence is broken and all questions are being answered. They're calling it their Extensible Processing Platform that takes advantage of ARM's dual-core Cortex-A9 MPCore processors, each running at up to 800 MHz. With the platform, designers can apply a combination of serial and parallel processing for applications that require high-speed access to real-time inputs, high-performance processing, and/or complex digital signal processing.
Thanks to the changes made in the architecture, a software-centric development flow is enabled by the processor-centric approach which presents a full processor system. This includes caches, memory controllers, and commonly used connectivity and I/O peripherals. It's built using Xilinx's high-performance, low-power 28-nanometer technology.
The high-bandwidth AMBA-AXI interconnects keep the programmable logic tightly coupled with the processor core. This architectural approach addresses common performance bottlenecks between these parallel and serial computing environments, memory, and I/O. It also gives the processor control of the programmable logic, including dynamic reconfiguration.
The architecture abstracts a lot of the hardware burden from software developers, who can now tap into the vast off-the-shelf open-source and commercially available software component libraries. Another key feature is the FPGA's ability to boot an operating system (OS) at reset.
Pricing and availability will be announced for products based on the Extensible Processing Platform architecture in early 2011.
==========
출처: http://www.embedded.com/products/integratedcircuits/224600510
2010년 4월 28일 수요일
묻지마식 무선랜 접속은 금물
해커 덫에 걸리기 십상...보안 10계명 생활화
2010년 04월 27일 (화) 18:26:27 / 장윤정 기자 linda@etnews.co.kr
▲ 무선랜은 접속이 손쉬운만큼 해킹, 개인정보유출, 분산서비스거부(DDoS) 공격 등 악의적인 공격의 표적이 되기 쉽다. 사진은 G밸리에 근무하는 직원들이 무선랜을 즐기는 모습.
‘수년전 H은행과 유사한 가짜 사이트를 통해 금융거래에 필요한 개인정보를 알아낸 뒤 12명으로부터 1억2000여만원을 가로챈 일당 3명이 구속된 바 있다. 당시 이들은 피싱 사이트 제작·설치부터 계좌에서 돈을 빼내는 모든 범행 과정에서 IP 추적이 어려운 무선랜을 이용했다.’
웬만한 대형 오피스 빌딩에 들어가면 무선랜 AP(Access Point)에 손쉽게 접속할 수 있고 공짜로 무선랜을 이용하는 등 무선랜 사용이 급속히 늘고 있다.
접속이 손쉬운 만큼 무선랜은 H은행 피싱 사이트 사고처럼 해킹·개인정보유출 (DDoS) 공격 등 악의적인 공격의 루트가 되기도 싶다.
방송통신위원회는 이러한 이유로 지난해 하반기 무선랜 공유에 대해 보안 문제를 이유로 AP에 암호와 패스워드 설정을 의무화하는 등 통신사업자와 사용자의 보안 의무를 강제화하는 법 제정 방안을 검토하기 위해 연구용역을 의뢰한 상황이다.
그러나 법 시행 여부를 떠나 사용자의 올바른 무선랜 사용이 금전 및 개인정보유출 사고를 막는 지름길이다.
커피숍·호텔 등 공공시설에 설치된 무선랜은 이용자 편의성을 우선하기 때문에 개인 ID 입력 등 이용자 확인만을 제공하고 암호설정을 하지 않는 경우가 많다. 암호 설정을 하지 않는 무선랜 환경에서는 개인정보 유출 등 피해의 우려가 있다.
특히, 인터넷뱅킹 등 민감한 애플리케이션 서비스는 사용하지 않는 것이 좋다. 자칫 개방된 무선 AP에 함부로 접속했다가 개인정보·금융정보 등의 불법 데이터 수집을 목적으로 피싱용 무선 AP를 설치하고 접속을 유도하는 해커들의 덫이 기다리고 있기 때문이다.
무선랜 사용자 인증과 암호화는 필수로 설정해야 하지만 무선 AP도 보안 관리해야한다. 무선 AP의 신호 세기를 줄여 필요 이상으로 넓은 범위까지 접속이 가능하도록 설정하지 않는 게 좋다. WPA-PSK 등 최신 암호기법을 이용해 노출되기 어려운 암호를 설정해야한다.
또한 무선 AP의 이름을 나타내는 SSID(Service Set IDentification)의 숨김 기능이 가능한지도 살펴봐야한다. SSID를 비공개로 하면 외부인이 무선공유기(AP) 존재유무를 확인할 수 없어, 무단 사용을 막을 수 있다.
그리고 무선AP를 사용하지 않는 시간에는 전원을 차단해 무단 접속을 막는 것도 중요하다. 외부 접속시 내 컴퓨터를 안전하게 보호하기 위해 운영체제에 기본 장착된 개인방화벽을 항상 켜둬야 한다.
스마트폰 사용시에도 무선랜 접속시 안전을 위해 스마트폰 백신 등을 설치해 악성코드, 바이러스 등을 진단치료해야 하고 블루투스는 사용시에만 활성화, 감염 위험을 낮춰야한다.
심종헌 유넷시스템 사장은 “스마트폰·인터넷 전화 등 무선랜 사용이 늘어감에 따라 안전하게 무선 인터넷을 이용하기 위해서는 사용자 스스로 무선 접속에 대한 관리가 필요하다”며 “해커에게 개인정보나 기업의 주요 데이터를 도난당하지 않기 위해서는 생활속에서 무선랜 사용 수칙을 제대로 지켜야 한다”고 말했다.
◇ 안전한 무선랜 사용 10계명
- 무선랜 사용자 인증과 암호화를 반드시 설정한다.
- 보안설정이 힘든 오래된 무선AP는 가능한 교체한다.
- 암호없는 무선랜 사용시에는 금융정보 등 주요정보 송수신은 삼간다.
- 와이파이 형태의 무선인터넷전화기 사용시 통신사업자가 제공하는 기본암호키를 반드시 변경, 설정한다.
- 무선AP의 전파 신호는 필요한 범위 내로 설정한다.
- AP의 이름을 나타내는 SSID를 숨기고 WPA-PSK 등 최신 암호화 기술을 사용해 공유기 무선 보안 관리를 철저히 해야 한다.
- 사용하지 않을 경우 AP의 전원을 차단한다.
- 무선랜 패스워드는 쉽게 추측하기 어려운 영문, 숫자의 조합으로 설정하며, 패스워드는 주기적으로 교체한다.
- 자신의 무선랜 접속계정이 다른 사람에게 노출되지 않도록 철저히 관리한다.
- 무선노트북의 개인방화벽을 설치, 항상 활성화시켜두어야하며 스마트폰에도 개인정보 유출을 방지하는 관리프로그램을 설정해둔다.
ⓒ 보안닷컴(http://www.boan.com) 무단전재 및 재배포금지 | 저작권문의
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2010년 4월 27일 화요일
Silego Technology Introduces GreenPAK: A Micro-FPGA with Programmable Analog
Earthtimes.org (Press Release)
Silego Technology Introduces GreenPAK: A Micro-FPGA with Programmable Analog
Posted on : 2010-04-26 | Author : Silego Technology, Inc.
News Category : PressRelease
SANTA CLARA, Calif. - (Business Wire) Silego Technology, Inc. announces the GreenPAK. GreenPAK is a 2x2 mm TDFN one-time programmable micro-FPGA with configurable analog components. GreenPAK (logic & analog) has been designed to operate as a stand alone IC capable of performing many 4-bit and 8-bit microcontroller applications or work in conjunction with Silego’s GreenCLK (timing) and GreenFET drivers (power sequencing) product lines to remove up to 25% of all components on larger computation and communication system boards.
GreenPAKs are configured with GreenPAK Designer 1.0 software and a USB-based GreenPAK programmer. The software is intuitive and its configuration requires no programming language or complier allowing a designer to configure, program, and test their custom GreenPAK in minutes.
GreenPAK, as a stand alone product, is targeted at many 4 and 8-bit microcontroller applications. The on-board finite state machine, logic, counters, delays, ADC, voltage reference, oscillator, and PWM allow for 1000’s of applications such as interface to sensors of all types, LED drivers, motor controllers, touch sensing, and over voltage protection.
GreenPAK is also the logic and mixed signal element of Silego’s Green product strategy for large computation and communication system boards. GreenPAKs remove power on resets, temperature sensor interface ICs, delay or timing related logic, glue logic, and power good circuits.
“Silego’s GreenPAK products are the first ICs that are able to cost effectively remove massive numbers of passive and simple active components from PCB designs improving reliability and reducing procurement issues while saving board area, power, and cost,” said John McDonald, Vice President of Marketing and Sales at Silego. “The success of the GreenPAK and its sibling, the GreenSAK product family, contributes to Silego’s vision of providing a comprehensive suite of ICs that clean up every PCB by reducing component count, simplifying design, and saving power and board space.”
Silego provides many options to learn about GreenPAK through live video web support 16 hour per day, training videos, software, or by scheduling one-on-one training session with a Silego application engineer to assist with GreenPAK development.
Prices and Availability
GreenPAK products are in volume production. Samples, datasheets and demonstration boards are available at www.silego.com. GreenPAK products are priced from $0.15 to $0.25 in moderate volume. Please contact Silego for ultra-high volume pricing.
About Silego
Silego Technology, Inc., founded in 2001, is recognized with the Deloitte Technology Fast 50 Rising Star ranking as one of the fastest growing technology companies in the Silicon Valley. Silego develops silicon solutions to reduce part count, power, and cost. Silego is the world’s largest notebook and netbook clock supplier and has numerous product lines that cover DDR3 register ICs, Consumer ICs, Notebook and Netbook ICs. Silego is headquartered in Santa Clara, California, with operations and design centers around the globe. Silego Technology is privately owned and backed by leading venture capital firms.
Silego Technology, Inc.
Tania Hryhorenko, 408-327-8800
Inside Sales Associate
taniah@silego.com
Press Release Print Source :
http://www.earthtimes.org/articles/show/silego-technology-introduces-greenpak-a-micro-fpga-with-programmable-analog,1266643.shtml
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Dust Networks Announces ARM Cortex-M3 Processor Based IEEE 802.15.4 SOC
D&R Headline News | Most Popular | SoC News Alerts | 
Dust Networks Announces ARM Cortex-M3 Processor Based IEEE 802.15.4 SOC
New benchmark for ultra-low power wireless sensor network performance
Hayward, CA, (April 26, 2010)--Dust Networks®, the leading supplier of wireless sensor networks (WSN), today announced that its new IEEE 802.15.4 products will include the powerful, low power ARM®Cortex™-M3 processor. Dust Networks' new family of system-on-chips (SoCs) will be the basis for a variety of upcoming standards-based WSN products, including IEC 62591 (WirelessHART™), 6LOWPAN (IP), and Zigbee ®PRO products that will provide unprecedented low power consumption while delivering a compelling set of energy saving, high performance features including:
- A 32-bit ARM Cortex M3 processor and rich interfaces enable a powerful computing platform while conserving power.
- The world's lowest power IEEE 802.15.4 radio: a new benchmark is set, with a mere 3 mA transmit at 0 dBm and 3 mA receive current, delivering 5-10 times the battery life of competing technologies, and further expanding the applicability of energy harvesting power sources.
- Extended range capabilities, with up to 8 dBm output power on-chip PA and an optional external power amplifier.
- The industry's first IEEE 802.15.4E-ready product, incorporating the emerging standard for time synchronization and channel hopping, while providing legacy support for 802.15.4-2006.
"Our new SoCs are geared to deliver the highest performance while running at a fraction of the power of competing silicon," said Dr. Kris Pister, Chief Technologist at Dust Networks. "In selecting the ARM Cortex-M3 processor for our SoC, we did not have to trade-off performance for power. Dust Networks new IEEE 802.15.4 SoCs will require less than one-tenth of the energy per operation of comparable SoCs."
The level of systems integration in the SoCs is very high, including on-chip power amplifier, DC-to-DC converter, 10 bit ADC and a built in temperature sensor. With configurations up to 512kB of flash and 72kB of RAM, these SoCs will have both the highest computational horsepower of any 802.15.4 chip on the market, and the lowest power consumption. In doze mode, with full processor state and RAM retention, current consumption is under 1uA.
"Dust Networks' adoption of the ARM Cortex architecture is a clear demonstration of the growing support for ARM Cortex-M3 processor-based for low-power applications " said Eric Schorn, VP marketing, Processor Division, ARM. "The ARM Cortex-M3 CPU is ideal for battery operated or energy harvesting designs where performance really matters and the feature-filled Dust SoC is a powerful example of what can be done with a 'green' approach to SoC design, in applications where every nanoamp counts. "
"Low power radios such as IEEE 802.15.4 and wireless mesh networking, epitomized by Dust Networks' TSMP protocol and its "Smart Dust" roots, have transformed the industrial wireless sensor network landscape" said Mareca Hatler, ON World research director. "With the introduction of ultra low power versions of SmartMesh IP (6LoWPAN) systems and ZigBee products, Dust Networks will expand the growing number of "Smart World" applications that span Smart Buildings, Cities, Government and Homes."
About Dust Networks
Dust Networks, the leader in standards-based intelligent wireless sensor networking (WSN), provides ultra low-power, highly reliable systems to OEMs. Dust Networks wireless technology enables unprecedented access to information from the physical world, in markets that range from industrial monitoring and control to emerging markets such as the Smart Grid, Smart Cities and Smart Buildings. Dust Networks' embedded products combine extremely low-power RF System-on-Chip (SoC) technology with revolutionary wireless networking capabilities, providing OEMs with a full range of standards-based WSN solutions that are flexible and easy to integrate. Dust Networks partners with industry and standards groups such as the HART Communication Foundation, IEEE, IETF, IPSO, ISA, SunSpec Alliance and the Zigbee Alliance to ensure the broad adoption of interoperable wireless sensor networking products.
About ARM:
ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes 32-bit RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com
All material on this site Copyright © 2009 Design And Reuse S.A. All rights reserved.
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출처: http://www.design-reuse.com/news/23242/arm-cortex-m3-processor-ieee-802-15-4-soc.html
2010년 4월 22일 목요일
Timing Closure on FPGAs
April 22, 2010
Sleep peacefully at night knowing that your design is in tip-top shape
By Nelson Lau, Spirent Communications
Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains.
While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures.
But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps.
In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.
The I/O Cell Structure
All FPGAs have I/O pins that can be highly customized. The customization affects timing, drive strength, termination and many other factors. When your I/O cell structure is not clearly defined, your tool chain will often use a default that may or may not be what you want. In the VHDL code below, the intent is to create a bidirectional I/O buffer named sda using the declaration "sda: inout std_logic;".
When the synthesis tool sees this block of code, there is no clear directive on how to implement the bidirectional buffer. As a result, the tool will take a best guess.
One way to accomplish the task would be to use a bidirectional buffer on the I/O ring of the FPGA (indeed, this is the desired implementation). Another option would be a tristate output buffer and input buffer, both implemented in lookup table (LUT) logic. A final possibility would be to use a tristate output buffer on the I/O ring along with an input buffer in an LUT—and this is the option that most synthesizers will choose. All three methods yield valid logic, but the last two implementations result in additional routing delays when the signal moves between the I/O pin and the LUT. They also require additional timing constraints to ensure timing closure. FPGA Editor clearly shows in Figure 1 that our bidirectional I/O has portions scattered outside the I/O buffer.
Click on image to enlarge.
The lesson? Don't let your synthesis tool guess how to implement critical sections of your code. Even if the synthesized logic happens to be what you want, it may change when the synthesis tool goes through a new revision. Clearly define your I/O logic and any critical logic. The following VHDL code shows how to implicitly define the I/O buffer using the Xilinx primitive IOBUF. Also note that all electrical properties of the buffer are likewise clearly defined.
In Figure 2, FPGA Editor clearly shows that our bidirectional I/O has been implemented entirely within the I/O buffer.
Click on image to enlarge.
Trials of Asynchronous Logic
Asynchronous code results in logic that is difficult to constrain, simulate and debug. Errors from asynchronous logic are often intermittent and nearly impossible to replicate. It's also not possible to generate a test bench to find errors due to asynchronous logic.
While asynchronous logic may seem easy to spot, in fact it often goes undetected, so designers must be aware of the many ways that asynchronous logic lurks in our designs. All clocked logic requires a minimum setup-and-hold time, and this also applies to the reset input of flip-flops. The code below uses an asynchronous reset. Here, there is no possible way to apply timing constraints to meet the setup-and-hold time requirements of the flip-flop.
The next listing uses a synchronous reset. However, the reset signal for most systems may be a pushbutton switch or some other source that is not related to the system clock. Although reset is mostly static, and asserted or deasserted for long periods, there is still a change in level. It is the deassertion of reset, relative to the rising edge of the system clock, that can violate the setup-time requirements of a flip-flop, and there is no way to constrain this.
Once we realize that we can't directly feed an asynchronous signal into our synchronous logic, the problem becomes easy to fix. The code below creates a new reset called sys_reset that has been synchronized to our system clock sys_clk. When sampling asynchronous logic, metastability issues can arise. We can reduce the chance of its occurrence by using a laddered sample that is ANDed with the previous stages of the ladder.
So, let's assume you've taken care to make all your logic synchronous. Nevertheless, if you're not careful, your logic can easily become decoupled from the system clock. Don't let your tool chain use local routing resources for your system clock. Doing so will make your logic impossible to constrain. Remember to clearly define all your important logic.
The VHDL code below uses the Xilinx primitive BUFG to force sys_clk onto a dedicated high-fan-out buffer that drives low-skew nets.
Some designs use a divided version of their single master clock to process deserialized data. The VHDL code below, process nibble_proc, shows an example of data being captured at one-quarter of the system clock rate.
It looks like everything is synchronous, but the nibble_proc uses a product term divide_by_4 to sample nibble_wide_data from clock domain sys_clk_bufg. Due to routing delays, there is no well-defined phase relationship between divde_by_4 and sys_clk_bufg. Moving divide_by_4 onto a BUFG will not help either, as the process incurs a routing delay. The solution is to keep nibble_proc on the sys_clk_bufg domain and use divide_by_4 as a qualifier, as shown below.
Importance of Timing Constraints
Applying the proper timing constraints is a necessity if you want your logic to perform properly. If you've taken care to ensure that 100 percent of your code is synchronous and all I/Os are registered, those steps will greatly simplify timing closure. Using the above code and assuming that the system clock is 100 MHz, the timing constraint file is easily done in four lines, as shown below.
Note that setup-and-hold times for I/O registered logic on Xilinx FPGAs are pretty much fixed and don't change much within a package. But we still apply them, mainly as a verification step to ensure that the design meets its system parameters.
Three Easy Steps
Designers will find that it's not hard to implement reliable code if they follow three simple steps.
- Don't let your synthesis tool guess at what you want. Use Xilinx primitives to clearly define all I/O pins and critical logic. Be sure to define the electrical properties of your I/O pins.
- Make your logic 100 percent synchronous and reference all logic to your master clock domain.
- Apply timing constraints to ensure timing closure.
If you follow these three steps, you will have removed variances due to synthesis and timing. Abolishing those two significant obstacles will give you code that works with 100 percent reliability.
This article was originally printed in Xcell Journal and reprinted here with the permission of Xilinx Inc. and Spirent Communications.
All materials on this site Copyright © 2010 EE Times Group, a Division of United Business Media LLC All rights reserved.
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2010년 4월 2일 금요일
The ISM Revolution: The Next Big Thing
February 09, 2009
By Iboun Taimiya Sylla, Texas Instruments
Editor's Note: This is the first part of a planned three-part series of articles from Iboun Taimiya Sylla. The second part is called: To ZigBee or Not to ZigBee? Factors to consider when selecting ZigBee Technology .
Imagine a farmer in the American Midwest facing the challenges of tracking the temperatures of 1000 head of cattle daily in order to prevent some animal diseases such as foot and mouth disease from decimating his herd. With wireless technology, such challenges can be easily overcome by simply attaching a temperature sensor equipped with a wireless transmitter on each cow, transmitting its reading to a main terminal. Such a method helps save time and the costs of dispatching crews for frequent and more often than not, unnecessary measurements. This illustrates the level of penetration of the low-power wireless devices operating in the ISM frequency band into everyday life (security, medical, industrial, agricultural, etc.). This penetration is being driven by three main factors:
- The desire to get rid of hardwired communications that are otherwise required for transmitting data over a long range.
- The allocation of the Industrial Scientific & Medical (ISM) frequency band by the regulatory bodies of various countries.
- The emergence of different wireless standards to offer interoperability in the ISM band.
Eliminating Wire Wherever and Whenever Possible
For a long time, hardwired communication has been the most reliable way of transmitting or receiving information between two points. Wired communication systems have been able to provide reliable transmission media as well as high speed along with a long life. While presenting many qualities, the wired solution presents limitations that tend to make it obsolete in favor of wireless technologies. Among these limitations are:
- Geographic: Depending on geography and terrain, wire becomes very challenging to install, especially in rural mountainous areas.
- Economic: The cost of the wired system is proportionally related to the length of wire required as in some cases repeaters are needed to compensate for the loss of signal strength. This implies that more cable translates into more costly solution.
- Comfort: When looking at today's consumer desires, dragging wire across certain places is highly undesirable. Therefore, wire systems are being considered as the last choice for consumers.
These three main limitations of wire transmissions explain the momentum gained by the wireless technology.
The Industrial Scientific & Medical (ISM) Band
The ISM band is a general purpose part of the radio spectrum that can be used without a license. The only requirement for developing products in the ISM band is compliance with rules governing this part of the frequency spectrum. These rules vary from country to country. In the US, the Federal Communication Commission (FCC) defines these rules, whereas ETSI is the governing body in Europe. Table 1 illustrated how FCC and ETSI have categorized devices functioning in the ISM band.
Table: 1 FCC and ETSI device Classifications
Systems designed in the ISM band are characterized by their low-power and low data rates. However, in recent years, data rates have been increasingly higher, challenging the designation of low data rates. Mostly used ISM bands are the 2.4GHz band and the sub-1GHz bands. Because of the cluttering in the 2.4GHz bands, some activities have been seen in the 5GHz band, but they remain very limited because of achievable range concerns. While the 2.4GHz is universal, the sub-1GHz bands allocated to the low-power wireless application vary from country to country. In the United States the most popular band remaining is the 902 " 928MHz band, whereas in Europe most activities are in the 868MHz. Understanding the fundamental differences between the 2.4GHz and the sub-1GHz band is an important factor when developing products in the ISM band.
The 2.4GHz band is recommended when interoperability with other systems is required as well as operation in different geographical spaces is a key target. Designing in the 2.4GHz presents two main challenges:
- Numerous wireless systems such as Bluetooth, Wi-Fi, 802.15.4, Zigbee and Microwave ovens operate in this band. Therefore, high interference levels pose a formidable challenge. The presence of these interference sources requires high frequency selectivity devices to ensure a good wireless link quality. Another efficient way to counter interference is to use techniques such as frequency hopping spread spectrum (FHSS) and direct sequence spread spectrum (DSSS) that provide more significant noise immunities.
- The second challenge of choosing the 2.4GHz lies in its achievable range. The 2.4GHz frequency tends to be absorbed more readily by the environment and surrounding objects, limiting the range. The rule of thumb is doubling the frequency of operation reduces the range by one half. It is worth noting that the range limitation can be overcome with the use of an external power amplifier (PA).
Choosing to design in the sub-1GHz band helps solve some of the issues faced in the 2.4GHz band; however, the sub-1GHz has its own limitations such as:
- The duty cycle in this band is restricted.
- Impossibility of achieving interoperability with other systems.
- Geographical limitation in the operation, for example: a wireless meter designed in the 902 " 928 MHz band for the US will not be able to operate in Europe.
Different Standards in the ISM Band
The last few years have witnessed the emergence of several wireless standards operating in the ISM band. These standards, along with proprietary solutions provide huge opportunities for developing a wide range of wireless products. These standards differ from each other by their data rates, communication ranges, application domains, as well as the modulation techniques used. Figure 1 illustrates the range versus data rate of several wireless standards.
1. Wireless Standard Operating in the ISM Band
Among the wireless standards cited on Figure 1, Bluetooth, Wi-Fi, Zigbee and IEEE 802.15.4 can be considered as the most prominent today. Most of these standards are operating in the 2.4GHz band.
- Bluetooth: This technology is based on the IEEE 802.15.1 standard. It is a wireless technology that enables devices to communicate in the 2.400 " 2.4835 GHz band. Bluetooth allows devices such as mobile phones, PDAs, printers, laptops and headsets to exchange data. It uses the Gaussian frequency shift keying (GFSK) type of modulation along with frequency hopping spread spectrum (FHSS). Three output power levels are available in the Bluetooth standards. Classes 1, 2 and 3 devices deliver 20dBm, 4dBm and 0dBm of output powers respectively. Recently, another variant of Bluetooth called Bluetooth Low Energy has been introduced by the Bluetooth SIG. Bluetooth Low Energy targets data exchange using lower power consumption than the earlier Bluetooth versions.
- Wi-Fi: As of today it represents the most prominent technology for wireless connectivity for computers and internet. Wi-Fi technology integrates most personal computers, PDA and other devices such as gaming and portable audio devices. Wi-Fi term is applicable to wireless devices that utilize the suite of IEEE 802.11 standard. Excepted 802.11b, WI-FI standard operates in the 2.4GHz band (2.4GHz " 2.4835GHz) and use FHSS and DSSS techniques. One area of concern of the 802.11 technology is the security of the network, as WLAN network can be penetrated by a third party.
- IEEE 802.15.4: Compared with Bluetooth and WI-FI/802.11, IEEE 802.15.4 targets low data rate application within the 868MHz, 915MHz and 2.4GHz bands. The number of channels and the data rates used in this standard vary with the chosen frequency band. The most popular frequency band is the 2.4GHz with 20 available channels with a maximum data rate of 250kbps. The primary target application of this standard is home automation, remote metering, gaming and wireless sensors networks. One key feature of the IEEE 802.15.4 standard is its low-power consumption ability, providing a long battery life (10 to 20 years).
- Zigbee: Built on top of the IEEE 802.15.4 PHY layer, Zigbee is a standard that utilizes the 802.15.4 standard. The 2.4GHz band remains the most used frequency band for Zigbee. To resolve the range and interference issue faced in the 2.4GHz, some companies are exploring the design of 915MHz Zigbee products. Unlike IEEE 802.15.4, Zigbee allows full mesh network. The announcement by utility companies of the deployment of several millions of Zigbee-based electric and gas meters has built a tremendous momentum for Zigbee and its smart metering applications.
In addition to the wireless standards presented above, the wireless industry is experiencing the emergence of several new standards that are in early development stages. On the other hand, many applications still remain proprietary as companies are concerned about compatibility with legacy products.
The world is experiencing a wireless revolution that is democratizing this very practical technology. Its use in all segments of life is not without problems for governing regulatory bodies that are at the center of more solicitations to make new frequency bands available. A careful and well thought out frequency spectrum management is required.
The second challenge highlighted by this revolution is the need of inventing new techniques to handle more interferers resulting from the crowdedness of the frequency spectrum.
About the Author
Iboun Taimiya Sylla manages business development for Low-Power RF products at Texas Instruments. Prior to his current position, Iboun was a Sr. RF Design Engineer. Iboun received his Bachelor in Telecommunication Engineering at ESPT, University of Tunis, Tunisia). He received his Master and Ph.D in Electrical Engineering from Ecole Polytechnique de Montreal, University of Montreal, Canada. He also holds a Master's in Business Administration with focus on Corporate Finance and Strategic Leadership from the University of Dallas, Texas.
Related Articles
- What Every RF Engineer Should Know: ZigBee
- Clearing the confusion on battery life and range for 2.4-GHz low power RF
- Implementing a processor-independent, battery-powered wireless mesh network
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출처: http://www.rfdesignline.com/showArticle.jhtml;?articleID=213000535
To ZigBee or Not to ZigBee? Factors to consider when selecting ZigBee Technology
March 13, 2009
By Iboun Taimiya Sylla, Texas Instruments
Editor's Note: This is the second part of a three-part series of articles from Iboun Taimiya Sylla. The first part is called: The ISM Revolution: The Next Big Thing.
The explosion of wireless technologies in recent years has allowed the emergence of several standards, especially in the Industrial Scientific & Medical (ISM) band. Among these emerging standards ZigBee is considered one of the most promising. Analysts are forecasting several hundreds of millions of ZigBee-enabled devices in coming years. Without a clear understanding of whether or not the ZigBee standard is the right fit for their application, many engineers have been developing new products based on the ZigBee platform. This article aims to help engineers answer a fundamental question when faced with selecting ZigBee technology: Is ZigBee the right technology platform for the next product to be developed?
ZigBee Platform Overview
The ZigBee standard is supported by a consortium of over 200 companies grouped under the name of ZigBee Alliance. The goals driving the ZigBee Alliance are the creation of a reliable, low-cost, low-power, open global standard for low data rate wireless solutions, while allowing multi-hop routing of data. The ZigBee standard through mesh network capability and AES 128-bit encryption provides support for self-healing and high security. Figure 1 describes a ZigBee network topology which typically includes three types of devices or nodes:
Coordinator : One coordinator exists in each network. It starts the network and handles management functions as well as data routing functions. These functions require that the coordinator always be powered. Therefore, this type of node is recommended to be main-powered.
Routers: In most cases, routers are also main-powered. They help carry data across multi-hop ZigBee networks including a variable number of routers and, in some cases, are without routers, thus, transforming the network into a point-to-multipoint.
End Devices: These are devices that are battery-powered due to their low-power consumption. They sleep most of the time and wake up regularly to collect and transmit data. Devices such as sensors are configured as end devices. They are connected to the network through the routers.
The type of node is assigned during the commissioning process. The main-powered requirement for coordinators can be a limiting factor for ZigBee, especially if minimizing power consumption is actively targeted for each and every device.
Figure 1. ZigBee Network Topology
As the number of nodes in a ZigBee network increases, potential communication bottlenecks can occur in some parts of the network. Two main techniques can be used to limit the congestion issue within ZigBee networks:
- Through node placement and adequate ZigBee router coverage within an installation area. This provides multiple paths for messages to reach a concentrator and alleviates potential bottleneck points in the network.
- Use several data concentrators instead of a single concentrator. This can reduce the number of hops required for nodes for their messages to reach a concentrator, and also reduces the chance of having a single point of failure.
In addition to the three methods mentioned earlier, techniques such as network partitioning through channel or PANID (or network ID) are available to deal with the ZigBee network congestion. These techniques, however, can be resource intensive.
Taking a close look at the ZigBee stack can help better understand challenges that implementing ZigBee can pose, especially when choosing a hardware platform. The ZigBee technology stack architecture has utilized the IEEE 802.15.4 standard, adding a set of layers to it to achieve the targeted features. Figure 2 describes the ZigBee stack architecture topology.
Figure 2: Architecture of the ZigBee Stack
Two lower layers, the physical layers (PHY) and the media access layer (MAC) are defined by the IEEE 802.15.4 specification. The PHY deals with the implementation of the direct sequence spread spectrum (DSSS) radio hardware in both 2.4GHz and sub-1GHz band, while the MAC handles access to the PHY layer. The above layers are defined by the ZigBee Alliance, except the application layer which is defined by the end user.
The layers defined by the ZigBee Alliance are respectively: the network layer, the application framework layer, and the application profile layer. The routing and the mesh capability are defined within the network layer. The security features implemented within the ZigBee stack are very flexible as it can be implemented in any of the layers. Security also can be defined for the application framework by the profile. The application profile plays a big role in the standard interoperability by helping implement a common data exchange protocol as well as a set of processing actions.
The application profile layer specifies the application domains and allows devices from different manufacturers to communicate with each other. Profiles for a specific application regroup different related ZigBee clusters library that specifies functional domains within that application. As of today, the ZigBee Alliance has defined three application profiles: Smart Energy, Home Automation and Personal Home and Hospital Care (PHHC). Several other profiles are expected to be completed in the near future. It is always possible for the users to implement their own profile, therefore, making the application proprietary.
The application layer in which the application code is implemented, is fully owned by the end user to control the specific application.
By analyzing the ZigBee stack architecture, you can appreciate its role when the end user chooses a processor. It is imperative that you use a high code efficiency, and large memory size processor when dealing with ZigBee in certain applications such as Smart Energy. The performance required from the processor can vary from one processor vendor to another for the same ZigBee stack. This factor should be carefully weighted during the ZigBee platform selection process.
To ZigBee or Not to ZigBee?
While ZigBee technology presents attractive features, several factors need to be analyzed before selecting the technology. A poor analysis of these factors could result in a very cost-inefficient product. Consider the following factors when selecting the technology process:
- Interoperability: The need for interoperability is a major factor in choosing ZigBee , especially when the product developed is expected to communicate with other manufacturer's devices. If interoperability is not required or desired, then a proprietary solution could be considered for the sake of cost efficiency.
- Power consumption: As the coordinator and routers in the network always need to be "ON," using the main power is highly recommended.
- Software overhead: ZigBee has the characteristic of high software overhead due to the stack size. ZigBee is not recommended for applications targeting very low CPU resource use such as CODE/RAM.
- Full mesh network: The benefit of the mesh configuration is to enable data exchange between points through multi-hoping link. A network of sensors in a large building could be a good example. In such a case ZigBee might be a perfect platform. However, a smart use of a star network provided by IEEE 802.15.4 standard or some other proprietary protocols can help route data at a cheaper cost.
Many engineers are snared by the attractiveness of the ZigBee technology, and possibly overlook solutions that could have helped design more cost-efficient products. In this article we presented an overview of the ZigBee technology as well as possible limitations. We also explained the main factors to considered, avoiding any pitfalls during the technology selection process.
References:
- To learn more about the ZigBee Alliance, visit: http://www.ZigBee.org/
- For more information about the IEEE 802.15.4 standard, visit: http://standards.ieee.org/getieee802/802.15.html.
- For more ZigBee solutions from Texas Instruments, visit: www.ti.com/ZigBee .
About the Author
Iboun Sylla is currently managing business development in the Americas for Texas Instruments Low Power RF products. Prior to this position, Iboun was a senior RF design engineer. Iboun received his Bachelor in Telecommunications Engineering from ESPT (Tunis-Tunisia), and his Master's and PhD in Electrical Engineering from Ecole Polytechnique de Montreal, Canada. Iboun also holds a Master's in Business Administration from the University of Texas at Dallas with focus on Corporate Finances and Strategic Leadership. Iboun can be reached at: ti_ibounsylla@list.ti.com.
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====================
출처: http://www.rfdesignline.com/showArticle.jhtml?articleID=215800324
Design Considerations for Robust, Low-Power RF Products (Part 3)
Understand the techniques you can use to minimize power dissipation while achieving performance goals
By Iboun Taimiya Sylla, Manager, Low-Power RF Business Development, Texas Instruments
RF Designline
(05/11/2009 7:00 AM EDT)
(Editor's Note: This is the third part of a three-part series of articles from Iboun Taimiya Sylla. The first part is The ISM Revolution: The Next Big Thing; the second part is To ZigBee or Not to ZigBee? Factors to consider when selecting ZigBee Technology.)
The Industrial Scientific & Medical (ISM) wireless revolution that created the transition from wireline to wireless has brought into sharp focus the vast market the wireless industry represents in today's economy. The combined wireless medical industry, automatic meter reading (AMR) and alarm & security represent an 18 billion-dollar market.
With the move from wireline to wireless comes a paradigm shift in system design considerations. The robustness of a wireless system is not characterized by the same parameters as the wireline systems. The robustness of a wireless system is primarily characterized by three parameters: power consumption, link quality and link security. In this article we will discuss these three parameters, as well as different techniques that can help an engineer improve the robustness of his design.
Power Consumption
Today, the end customer's satisfaction depends largely on power consumption, among other things. Low-power consumption translates into longer battery life and, therefore in the long run, a cheaper system. In the wireless e-meter industry, it is common to target an average battery life of 20 years. One can clearly say that power consumption is a key parameter that wireless product designers need to keep in mind, unlike with wireline systems where power consumption is of little concern because the system is mains-powered. We suggest three techniques than can help the designer optimize the power consumption of his product:
- Use low-duty cycle: We recommend minimizing the transmitter's (TX) and receiver's (RX) "on time" by sending just the amount of data needed. A way to achieve this is to use high data-rate transmission. Keep in mind that using high data rates requires a trade off on the achievable link range. High data rates yield less range for two main reasons: less energy per bit makes demodulation more difficult; and the RX filter bandwidth must be wider, therefore, allowing the presence of noise.
- Use FIFO register at RX and TX: For example, using the CC1101 (a low-power, sub-1 GHz RF transceiver) , or the CC2500 (a low-power, 2.4 GHz RF transceiver), the presence of a FIFO register allows burst mode data transmission with a high over-the-air data rate, which helps to reduce overall power consumption. If transmitting 10 kbps data using an over-the-air data rate of 100 kbps, the TX or RX contribution to the overall power consumption is reduced to approximately one-tenth, compared to 10 kbps. It is important to know that when over-the-air data rate is increased, sensitivity might drop due to less energy per bit and wider RX channel filter bandwidth.
- Implement receiver polling: The RX goes to sleep and wakes up periodically to see if any packets need processing. Given the short awake time the average current consumption is minimal. This helps to reduce power consumption and thereby significantly extends the system's battery life. Figure 1 illustrates an example of a receiver polling implemented on a highly integrated multichannel RF transceiver such as the CC1100. Notice the time distribution of the current consumption. This technique of programmable wake ups, receives and sleep times offers some flexibility on the battery life.
Figure 1: Current consumption time distribution in the receiver polling implemented on the CC1100
(Click on image to enlarge)
The link quality of a wireless system is mainly dependent on three key factors: the transmitter's output power; receiver sensitivity; and the propagation environment, which includes the level of interference, especially when targeting the 2.4 GHz band. Output power and sensitivity are two parameters that a design engineer can control. Using an external power amplifier and low-noise amplifier can help improve these parameters and, ultimately, the link budget.
The most critical part of the link quality is the propagation environment, especially when facing the challenge of increasing the immunity to numerous interference sources. With several applications (Bluetooth', Wi-Fi', ZigbeeTM, 802.15.4, microwave oven, etc.) using 2.4 GHz band, designing in that band presents a serious challenge, as you have to ensure that the design is robust enough to be jammed by external signals. To help against this type of interference, spread spectrum modulation techniques are widely used and have proven to be very efficient.
These techniques consist of spreading the energy across a number of frequency-band channels. They reduce output and power spectral density and help limit the interference on other users in the band.
The Federal Communication Commission (FCC) allows wireless systems using spread spectrum techniques to output more power. There are two spread spectrum techniques:
- Frequency hopping spread spectrum (FHSS): as depicted in Figure 2, to lower the average power spectral density. Frequency hopping utilizes a predetermined set of frequencies with either a repeating hop pattern or a pseudorandom hop pattern. Note that FHSS is also used in military applications to prevent eavesdropping.
Figure 2: Frequency hopping spread spectrum technique
(Click on image to enlarge) - Direct sequence spread spectrum (DSSS): illustrated in Figure 3, DSSS spreads its energy by rapidly phase-chopping the signal in such a way that each bit is represented by multiple bits using spreading code.
Figure 3: Direct sequence spread spectrum technique
(Click on image to enlarge)
Frequency agility techniques are also used against interference when working on a robust system. As illustrated in Figure 4, frequency agility can be considered as an extremely slow frequency-hopping system. The frequency is changed when the link performance is degraded and the measured packet error rate (PER) exceeds a predetermined threshold.
Remember that in both FHSS and frequency agility techniques, the phase-locked loop (PLL) lock time is very critical, as the system needs to hop to the next frequency in a very short period of time.
Figure 4: Frequency agility technique
(Click on image to enlarge)
Another technique that helps maintain the quality of the wireless link is to implement forward error correction (FEC). This method helps reduce the effect of bit errors in the packets. With the FEC, a bit error doesn't necessarily result in a packet error.
Link Security
Usually, the two most important aspects of wireless link security are preventing eavesdropping and preventing an attacker from inserting his own packets in the link. To solve these issues, the designer has access to advanced encryption standard (AES) and the asymmetric cryptography.
The AES algorithm uses one of three cipher key strengths: a 128-, 192-, or 256-bit encryption key (password). Each encryption key size causes the algorithm to behave slightly different, so increasing key sizes not only offers a larger number of bits with which you can scramble the data, but also increases the complexity of the cipher algorithm. The asymmetric cryptography allows the keys to be encrypted and is much more processor-intensive. Therefore, it is usually used only to encrypt keys.
Conclusion
In this article we have discussed the main design considerations for a robust RF product. Power consumption, link quality, and link security are the main parameters that characterize the robustness of a wireless product. These parameters must be at the forefront of any consideration. They can not be ignored without affecting the robustness and consequently the reputation of the product.
References
·For more information about low power RF and Zigbee solutions, click http://www.ti.com/zigbee-ca.
About the Author 
Iboun Sylla is currently managing business development for low-power RF products for Texas Instruments. Iboun brings to this role his extensive experience as a Sr. RF Design Engineer. Iboun received his Bachelor in Telecommunications Engineering from ESPT (Tunis-Tunisia), and his Master's and PhD in Electrical Engineering from Ecole Polytechnique de Montreal, Canada. Iboun also holds a Master's in Business Administration from the University of Texas at Dallas with focus on Corporate Finances and Strategic Leadership. Iboun can be reached at ti_ibounsylla@list.ti.com.
====================
출처: http://www.rfdesignline.com/showArticle.jhtml?articleID=217201195
Power detection and control for mobile handsets
Understand the various biasing methods and tradeoffs in GSM/EDGE mobile unit PA stages
By David Ripley, Technical Director, Skyworks Solutions, Inc.
RF Designline
(06/08/2009 7:00 AM EDT)
A key requirement within the modern mobile-handset power amplifier (PA) is a need to detect and control the transmitted power. This three-part article first explores the various methods of power control for amplifiers operating in both saturated and linear modes. The discussion continues with power detection techniques used in modern handsets. Topics include current, voltage, diode, power, logarithmic (log), and RMS detection, including performance characteristics such as RF bandwidth, video bandwidth, dynamic range, temperature compensation, and VSWR insensitivity.
This three-part series examines the subject as follows:
- Part 1: Power amplifier biasing for power control (click here)
- Part 2: Power detection methods (click here)
- Part 3: Power control feedback (click here)
David S. Ripley received his B.S. degree in electrical engineering from Iowa State University, Ames, in 1992 and the M.S EE degree from National Technical University (NTU), Minneapolis, MN, in 2002. From 1992 to 1999, he worked in the Cellular Subscriber Division, Motorola, Libertyville, IL, where he was involved in the design and development of TDMA and AMPS handsets including RFIC design of receiver and synthesizer functions. Since 1999, he has been with Skyworks Solutions, Inc. (previously Conexant Systems, Inc.), Cedar Rapids, IA, where he has been involved with the design of multiband HBT power amplifiers modules for the GSM and CDMA cellular handsets. He holds seven patents.
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