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Designers use several design techniques to significantly reduce overall system power consumption, such as:
* Reducing operating voltage;
* Optimizing system and CPU clock frequency;
* Eliminating spikes of large current consumption during the power up sequence;
* Efficiently managing system battery operation;
* Efficiently managing operating mode of system devices;
* Minimizing bus activity;
* Reducing bus capacitance;
* Reducing switching noise.
Many manufacturers today offer devices with power saving modes that temporarily suspend the device from its normal operation. These devices have the option to power down or transition to a non-functioning state if the device is not active for a specific amount of time.
This feature is available on many of today's microprocessors and MCUs. By taking advantage and managing the operating mode of large power consumers on a PCB, such as the processor, the overall power consumption of the system can be reduced significantly.
Reducing power consumption involves correct management of the operating mode of a device and designing a system to take advantage of the modes a device can operate within.
Offloading operations of the microprocessor allows it to stay in its low-power state for a longer amount of time. One way to reduce system power is to allow a low-power PLD, such as a CPLD, to manage these offloaded operations.
This article describes this possibility, along with types of operations that allow a processor to remain in a low-power state longer, thereby reducing system power consumption.
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| Figure 1: Shown is the typical power consumption of system components in a Web Pad application. |
Microprocessor modes
In some portable applications, the CPU can consume 30 percent of the overall system power. Figure 1 above illustrates the typical power consumption of system components in a Web Pad application.
Microprocessor power consumption can range from 720µW to 1W during normal operation. Microprocessor operating modes vary by part and manufacturer and include modes such as normal; run, sleep, suspend, standby, stop and idle operation.
Operating modes can vary in power consumption as much as 230mW between states. Normal operation of some low-power microprocessors can be as little as 250mW.
Figure 2 below illustrates the power consumption of the Intel StrongARM SA-1110 microprocessor operating modes. The power dissipation numbers shown in Figure 2 are determined by operating at 206MHz with a nominal external voltage supply of 3.3V and internal voltage supply of 1.8V.
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| Figure 2: Shown is the difference in power consumption of operating modes in a microprocessor. |
Operating modes of the StrongARM processor include normal, idle and sleep. In normal operation, the CPU is full-on, with the device fully powered and receiving active clocks.
In idle mode, even though power is applied to the CPU and other components, all clocks to the CPU are stopped, with only clocks to peripheral devices active. In sleep mode, power to the CPU and other peripheral components is disabled. Sleep mode disables all functions except the real-time clock, interrupt controller, power manager and general purpose I/O.
Microprocessors with power saving modes have an on-board power management controller. Operating modes allow the OS or software application to temporarily suspend the CPU. The microprocessor executes a series of instructions to place itself into a power saving state. Once in a power down mode, several components of the microprocessor can still respond to system interrupts.
Idle and sleep modes
For example, the idle mode of the StrongARM SA-1110 processor saves significant power, but certain modules remain powered, such as the LCD, memory and I/O controllers. Even though the clock to the CPU is stopped, peripheral modules are still active.
The idle mode can still consume a significant amount of power, on the order of 100mW. By placing the processor into the sleep mode, only active modules are powered to respond to interrupts and wake up signal requests.
Sleep mode consumes even less power than idle mode; current consumption can be less than 100mA. For a microprocessor to return to normal operation from a power down mode, an event must occur.
The following events can wake up the processor, but vary based on manufacturer, part, and current operating mode:
* Hardware reset;
* System interrupt;
* GPIO interrupt;
* Real-time clock interrupt; * OS timer interrupt;
* Peripheral interrupt;
* External wake-up signal.
Upon recognition of an enabled wakeup event, the microprocessor will begin a series of steps to wake up from a power down state. Figure 3 below illustrates the general flow for a processor waking up from a power down mode.
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| Figure 3: Shown is the general flow for a processor waking up from a power down mode |
CPLD design
Operating modes are using when the microprocessor is idle for a specific amount of time. When a microprocessor receives an enabled interrupt, the processor will respond to the interrupt request.
When the processor is responding to the interrupt, it will operate in its run or normal mode. Reducing the number of interrupts to the processor will increase the time the processor is in a power saving state. Ideally, if the microprocessor does not have any instructions to execute, it will remain in a power saving mode forever.
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| Figure 4: Using an external data acquisition device to offload interrupt requests required of the microprocessor will reduce overall system power. |
Inserting an external device to respond and handle system interrupts can reduce the operations required of the processor. By allowing the microprocessor to stay in its power down mode as long as possible, significant power savings can be realized.
Using a low-power PLD to supplement the microprocessor will save system power and increase system battery life. The industry's latest CPLD offerings simultaneously deliver high performance and low power consumption.
Standby current of a typical low-power CPLD is less than 100µA. Figure 4 above illustrates using a reprogrammable CPLD to interface to incoming system interrupts. Using an external data acquisition device to offload interrupt requests required of the microprocessor will reduce overall system power.
System interrupts
Depending on the end application for the processor, a variety of external devices may interrupt the processor. These interrupts include both data acquisition and data processing requests.
By separating data processing interrupts to the microprocessor, data acquisition interrupts can now be serviced by the external CPLD. Utilizing a CPLD to handle data acquisition interrupts will offload interrupt requests to the microprocessor and save power.
Categorization of the type of data acquisition interrupts to the CPLD will depend on the end application. Peripheral devices or incoming data demanding a response to incoming data can be classified as data acquisition interrupt requests. Data acquisition interrupts include:
* Memory access interrupts;
* Communication interfaces such as I2C, UART, SPI or ISA;
* GPIO interrupts;
* LCD interface interrupts.
This is not a complete list of interrupts that can be processed by the CPLD, but provides a starting point for the system design.
Operational flow
Figure 5 below illustrates the main operational flow for the design of a CPLD. Once a valid external interrupt is recognized by the CPLD, it will determine if it contains the functionality to process the interrupt.
Once the CPLD has processed the interrupt, it can assert an interrupt to the processor for any data processing requests needed. If the CPLD is unable to process the interrupt, the interrupt is passed to the processor. The CPLD also monitors the operating state of the processor.
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| Figure 5: Shown is the main operational flow for the design of a CPLD |
Functionality
The low-power CPLD design consists of an interrupt interface and controller to handle interrupt requests, the functionality to process the interrupt, and a processor interface. The main functions of the CPLD are as follows:
Interrupt interface. The interrupt interface of the CPLD receives all external device interrupt requests previously recognized by the microprocessor. The interrupt interface determines if the CPLD is capable of processing the interrupt request. The CPLD handles data acquisition interrupts that request data receiving and storage capabilities.
If the CPLD is unable to process the interrupt, the interrupt is passed to the microprocessor. The CPLD interrupt interface provides the masking capability for all interrupt sources and the ability to determine the interrupt source.
Programmable logic provides flexibility to change the trigger mode, which includes a high or low level and falling or rising edge sensitivity. The CPLD interrupt control registers are similar to the registers in the microprocessor.
Interrupt controller. The CPLD interrupt controller emulates the functionality that exists in the system microprocessor. The interrupt controller interprets from which device the data acquisition interrupt was received and initiates the processing of the interrupt.
The CPLD processes the data acquisition interrupt request that would have otherwise interrupted the microprocessor. The interrupt controller initiates the action to process the request. An example of this is an application where the CPLD is receiving data from a remote device.
The device is requesting to write the data being sent into memory. The CPLD interrupt controller recognizes a valid interrupt and initiates the memory interface to interpret the data. Peripheral device interfaces—The CPLD provides the interface to system devices that are needed in processing interrupt requests. Device interfaces that are needed are dependent on the end application.
When an external device interrupts the CPLD to read or write data into a memory component, that particular memory interface is needed in the CPLD design. The types of interfaces needed can range from memories to LCD interfaces to communication interfaces such as PCI, UART, SPI and ISA.
Microprocessor interrupt interface. The CPLD, like any external device requesting services of the processor, has the capability to interrupt the microprocessor.
The CPLD must be able to interrupt the microprocessor once a data acquisition operation is complete. The designer has the option to set the priority level of interrupt requests from the CPLD and whether or not interrupts received from the CPLD will wake the processor from a power down state.
Microprocessor operating mode interface. Depending on the system microprocessor, the CPLD will be able to recognize the operation state of the processor. Some microprocessors provide external pins that represent the current operating mode.
Depending on the CPLD and microprocessor design, the CPLD could recognize the current operating state of the processor and determine whether to assert an interrupt to the processor to execute a waiting interrupt.
For example, if a low priority interrupt is received by the CPLD and the processor does not need to transition from its low-power state, the CPLD can create a register indicating pending interrupts. Then when the processor wakes, the interrupt pending register can be read by the microprocessor.
Benefits
Figure 6 below illustrates the power savings that may be realized in a typical battery operated device using a leading-edge, low-power CPLD (left) vs. a standalone microprocessor design. The power requirements of the CPLD are minimal compared with the power savings realized by keeping the microprocessor in its low-power modes for a longer amount of time.
Standby current of a typical low-power CPLD is on the order of 100µA. The operating power consumption depends on the application and clock frequency.
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| Figure 6: Shown is the power savings that may be realized in a typical battery operated device using a leading-edge, low-power CPLD (left) vs. a standalone microprocessor design (right). |
For a 64-macrocell CPLD fully populated with 16bit counters and a 50MHz clock, ICC is around 10mA. Note that the actual power savings realized will depend on the system design, including the type of microprocessor and the CPLD design.
Along with power savings attained using a CPLD, interrupt response time is reduced. The peripheral device no longer has to wait the delay time for the microprocessor to wake from a power saving state.
Additional design savings that can be realized include:
* Reducing the number of interruptions to the processor;
* Reducing the number of processor wake-up cycles over a length of time;
* Reduction of clock frequency without impact on throughput;
* Running the processor at a lower frequency for data processing operations;
* Running the CPLD at a higher frequency for data acquisition operations.
Designing a power-sensitive application involves not only using software for power management, but utilization of hardware design techniques. Designing a low-power CPLD to keep a microprocessor in a low-power operating state longer can significantly reduce system power consumption.
Mark Ng is an Applications Engineer at Xilinx Inc.
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