- Exploiting Circuit Emulation for Fast Hardness Evaluation
P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
IEEE Transactions on Nuclear Science, Vol. 48, No. 6, December 2001, pp. 2210-2216 - A new functional fault model for FPGA Application-Oriented testing
M. Rebaudengo, M. Sonza Reorda, M. Violante
DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 372-380 - An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits
P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
Journal of Electronic Testing:Theory and Applications, Vol. 18, No. 3, June 2002, pp. 261-271 - An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
M. Rebaudengo, M. Sonza Reorda, M. Violante
DATE2003: Design, Automation and Test in Europe, 2003, pp. 602-607 - Analyzing SEU Effects in SRAM-based FPGAs
M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori
IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 119-123 - Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2088-2094 - Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella,, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193 - On the evaluation of SEU sensitiveness in SRAM-based FPGAs
P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante
IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 115-120 - A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
F. Corno, J. Perez, M. Sonza Reorda, M. Violante
SBCCI04: IEEE Symposium on Integrated Circuits and Systems Design, 2004, pp. 71-75 - Coupling Different Methodologies to Validate Obsolete Microprocessors
L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
DFT'04: The 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study
L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
XIX Conference on Design of Circuits and Integrated Systems, Bordeaux, France, November 24-26, 2004 - On-line Analysis and Perturbation of CAN Networks
M. Sonza Reorda, M. Violante
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004, pp. 424-432 - Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella
IEEE Transactions on Nuclear Science, Vol. 51, No. 6, December 2004, pp. 3354-3359 - On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs
F. Kastensmidt, L. Sterpone, M. Sonza Reorda, L. Carro
DATE2005: IEEE Design, Automation and Test in Europe, 2005, pp. 1290-1295 - Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
M. Sonza Reorda, L. Sterpone, M. Violante
ETS2005: IEEE European Test Symposium, 2005, pp. 136-141
BEST PAPER AWARD at IEEE ETS 2005 - Efficient Estimation of SEU effects in SRAM-based FPGAs
M. Sonza Reorda, L. Sterpone, M. Violante
IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 54-59 - RoRA: Reliability-oriented Place and Route for SRAM-based FPGAs
L. Sterpone, M. Sonza Reorda, M. Violante
PRIME05: IEEE Ph.D. Research In Micro-Electronics & Electronics, 2005, pp. 147-150 - Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
L. Sterpone, M. Violante
IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 5, October 2005, pp. 1545 - 1549 - A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
L. Sterpone, M. Violante
IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 6, December 2005, pp. 2217 - 2223 - A design flow for protecting FPGA-based systems against single event upsets
L. Sterpone, M. Violante
DFT2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 436 - 444 - A new approach to compress the configuration information of programmable devices
L. Sterpone, M. Violante, M. Martina, G. Masera, A. Molino, F. Vacca
DATE2006: IEEE Design, Automation and Test in Europe, 2006, pp. 1 - 4 - A Fault Injection Environment for SoPC's Embedded Microprocessors
M. Portela-Garcia, L. Sterpone, C. Lopez-Ongil, M. Sonza Reorda, M. Violante
LATW2006, 7th IEEE Latin-American Test Workshop, pp. 68-73 - A new approach to cope with single event upsets in processor-based systems
M. Schillaci, M. Sonza Reorda, M. Violante
LATW2006, 7th IEEE Latin-American Test Workshop, pp. 145-150 - A New Hybrid Fault Detection Technique for Systems-on-a-Chip
P. Bernardi, L. M. Veiras Bolzani, M. Rebaudengo, M. Sonza Reorda, F. L. Vargas, M. Violante
IEEE Transactions on Computers, Vol. 55, No. 2, Feb. 2006, pp. 185-198 - A new reliability-oriented place and route algorithm for SRAM-based FPGAs
L. Sterpone, M. Violante
IEEE Transactions on Computers, Vol. 55, No. 6, June 2006, pp. 732 - 744 - Fault Injection-based Reliability Evaluation of SoPCs
M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena
ETS2006: IEEE European Test Symposium, 2006, pp. 75 - 82 - An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs
L. Sterpone, M. Violante, S. Rezgui
IEEE Transactions on Nuclear Science, Vol. 53, Issue 4, August 2006, pp. 2054 - 2059 - Hardening FPGA-based systems against SEUs: A new design methodology
L. Sterpone, M. Violante
Academy Publisher Journal of Computers, Vol. 1, No. 1, April 2006, pp. 22 - 30 - Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs
M. Sonza Reorda, L. Sterpone, M. Violante, F. Lima Kastensmidt, L. Carro
[Accepted for publication on] JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers - Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro’s PowerPC 405
P. Bernardi, L. Sterpone, M. Violante, M. Portela-Garcia
[Accepted for publication on] IEEE Transactions on Nuclear Science, 2006, Vol. x, No. y, December 2006, pp. z - w | |
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