Emailing: SYSTEM SYNTHESIS OF DIGITAL SYSTEMS

http://www.ida.liu.se/~petel/SysSyn/

 

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SYSTEM SYNTHESIS OF DIGITAL SYSTEMS

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Goal

Gives the basic knowledge about modern design methods for digital systems.

Organization:

There will be nine lectures given by the teachers.
Additional lectures will be dedicated to presentation of term papers (case studies) by the students.

Literature:

P. Eles, K. Kuchcinski and Z. Peng "System Synthesis with VHDL" published by Kluwer Academic Publisher, December 1997.

Examination:

Term paper and seminar presentation.

Credits:

3 points.

Teachers:

Petru Eles, tel 28 13 96, e-mail petel@ida.liu.se.
Zebo Peng, tel 28 40 46, e-mail zebpe@ida.liu.se

Lecture Plan:

• Thursday March 23, 10-12 in Elogen:
  Introduction and Course Overview. System Synthesis and High-Level Synthesis (Petru Eles).
  lecture notes
  
• Thursday April 6, 10-12 in Elogen:
  VHDL - Basics and Simulation Mechanism (Petru Eles).
  lecture notes
  
• Thursday April 13, 10-12 in Elogen:
  High-Level Synthesis (Zebo Peng).
  lecture notes
  
• Thursday April 20, 10-12 in Elogen:
  Basics of Transformational Approach (Zebo Peng).
  lecture notes
  
• Thursday April 27, 10-12 in Elogen:
  Optimization Heuristics for Synthesis (Zebo Peng).
  
• Thursday May 11, 13-15 in Elogen:
  System-Level Synthesis and Hardware-Software Partitioning - I (Petru Eles).
  
• Thursday May 18, 10-12 in Elogen:
  System-Level Synthesis and Hardware-Software Partitioning - II (Petru Eles).
  
• Wednesday May 31, 10-12 in Eliten:
  Synthesis of Advanced Features (Petru Eles).
  
• Thursday June 8, 10-12 in Elogen:
  High-Level Synthesis for Testability(Zebo Peng).
  
• Thursday June 15, 10-?? in Elogen
  Presentation of Term Papers.

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20-April-2000 21:22