Swedish start-up details programmable WiMax baseband chip

By Nicolas Mokhoff

Courtesy of EE Times (02/04/2008 8:38 AM EST)

SAN FRANCISCO — At the International Solid State Circuits Conference here this week a Swedish start-up will detail a fully programmable baseband processor for mobile wireless applications. The design enables standards such as mobile WiMAX and DVB-T/H to be implemented more efficiently than in fixed function circuits.

In a paper to be delivered here on Tuesday (Feb. 5), the co-founders of Coresonic AB will outline the processor architecture that forms the basis of Coresonic's LeoCore semiconductor IP. It is optimized for WiMAX and 4G wireless modems.

Authors Anders Nilsson and Dake Liu, professors at the Linkping University in Sweden, developed the architecture at the university. Along with Coresonic's Eric Tell and Christer Svensson, they have now applied it in a commercial environment.

"We were able to implement the processor in a laboratory environment, without any specific power management circuits, to achieve 70mW at 70 MHz at the highest data rate of 31.67 Mb/s in DVB-T/H. In a commercial environment, with power management sub-systems added, we have used this architecture to significantly improve the power consumption and make it highly competitive compared to other implementations of wireless baseband processors," said Liu, who is also CTO of Coresonic.

Their single instruction, multiple tasks architecture exploits the characteristics of baseband algorithms to reduce the control overhead and improve the memory utilization compared to very-long instruction work (VLIW)/single-instruction, multiple data (SIMD)-based baseband processors. The LeoCore technology issues only one instruction for each clock cycle but allows several operations to execute in parallel as vector instructions run for several clock cycles on the SIMD units.

Using the technique, memory efficiency increased and an entire DVB-T/H implementation fit within the program memory of 2-K words.

VLIW and SIMD architectures have have been used to achieve the high computing capacity required in baseband processing. According to the authors, the drawback of VLIW-based architectures is their low power efficiency caused by wide instructions that need to be fetched during each clock cycle. On the other hand, SIMD-based DSPs lack the ability to perform different concurrent operations, leading to low data-path utilization.

According to the authors, a programmable processor architecture enables hardware reuse not only between different radio standards but also between different parts of the processing flow. Through hardware multiplexing, a programmable solution uses a smaller silicon area than a hardwired version--even for a single standard. Smaller silicon also results in lower power consumption due to reduced leakage and on-chip communication power.

Coresonic's architects used a 0.12-micron CMOS process to produce a chip that occupies an area of 11-mm2, which includes 1.5 Mb of single port memory and 200,000 gates.

"Because our results are so efficient, companies can choose to implement the technology in cheaper technologies or at very low voltages, enabling them to make the best design trade-offs for their end products," said Coresonic CEO Rick Clucas.

Coresonic was founded in 2004 as a spinout from the Stringent research center at Linkping University.

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