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- 출처: http://www.edn.com/article/CA6565881.html?industryid=47039

SiliconBlue launches company with new low-power FPGA

By Ron Wilson, Executive Editor -- 6/2/2008
EDN

SiliconBlue, a quiet startup with heavy FPGA-industry credentials, will go against the odds today by announcing its first product: a moderate-sized, moderate-performance FPGA family intended to be low enough in power and cost to be used in cellular handsets and other mobile devices. It's an audacious business move and an audacious claim, with some interesting technology behind it.

The company is claiming no huge breakthroughs in FPGA architecture or in process technology. In fact, according to founder and CEO Kapil Shankar, the SRAM-based logic fabric will look quite familiar to users of Spartan or Cyclone mid-sized FPGAs from the big guys.

"We didn't invent a new architecture here," adds the company's vice president of strategic marketing, industry insider John Birkner. "Our logic cell uses a four-input lookup table and a register, with a bypass path. It's actually based on the now-expired Xilinx patent from 1986." And SiliconBlue is fabricating its devices in TSMC's 65LP logic process, without significant modifications.

But the company is claiming significant reduction in power, saying that a 3500-logic-cell device can operate at 32 MHz while drawing only 9 mA from its 1.2V supply. The entire question of FPGA power consumption is hugely complex due to the lack of benchmarks, the wide array of activity profiles, various kinds of standby and sleep modes, and architectural approaches to reducing clock frequency that become factors in comparing power. But it does appear at first look that the SiliconBlue parts are showing significantly lower operating power on similar tasks than their mainstream competitors. The company claims similar advantage on standby power.

So where is the advantage coming from? The simple answer is that the SiliconBlue devices have been designed from a clean sheet of paper to exhibit low power in moderate-speed applications. It’s not a matter of a single silver bullet, but rather a consistent approach to a goal.

This drive starts at the process level, according to Shankar. SiliconBlue uses vanilla CMOS, allowing the company to benefit immediately from low operating voltage. The fact that the chips are designed for moderate performance—they only have to be faster than competing ultralow-power FPGAs, not faster than the latest 10W bleeding-edge parts—allows SiliconBlue to choose low operating voltage on low-leakage libraries at 65 nm and still meet performance goals. The company also made judicious choices in transistor sizing and doping to further reduce power.

Circuit design plays a role too, Shankar says. The company designed the all-important lookup tables with complementary logic rather than the faster n-channel circuitry. Designers used register macros rather than SRAM macros for memory on the chips, again reducing both static and dynamic power. And they provided power-down circuitry for both multiplexers and interconnect links that are not in use. "We had a lot of circuit flexibility because we had this inherent speed advantage compared to the older processes other low-power products use," Shankar observes.

All of these factors should give the devices a significant power advantage over other moderate-sized FPGAs using significantly larger geometries in order to accommodate flash or antifuse technology. But what about direct comparison to the latest 45-nm-node parts that will be coming from Altera and Xilinx? SiliconBlue points to one more significant difference that distinguishes its offerings from these parts: the SiliconBlue FPGAs require no external configuration memory.

Conventional SRAM-based FPGAs are of course volatile: they lose their configuration shortly after the power goes down, and must be reloaded from an external memory on power-up. This consumes time and energy—especially when dealing with the power-on inrush currents of the devices—and it seriously limits the degree to which the FPGAs can be power-gated during operation. It also requires additional board space. Some users have circumvented the latter problem with mutlidie packaging, stacking the configuration flash die on top of the FPGA at some additional cost.

In contrast, the SiliconBlue parts also configure themselves at power-up, but they have a configuration memory on the die, as a one-time-programmable ROM array. The chips are designed to use either external configuration memory or the internal ROM, based on a switch setting. Using the internal ROM, the FPGAs load a configuration without a lot of external electrical activity.

To implement the internal ROM without incurring the penalties of a non-standard process, SiliconBlue uses a logic-compatible, 1.5-transistor oxide-disruption ROM cell technology derived from work done at Kilopass. "Our technology started there, but split off from theirs as the companies went different directions," Shankar explains. The entire configuration memory for a SiliconBlue device occupies about 2.5% of the die area, according to Shankar. There is an on-chip 6.5V bias generator for programming the one-time-programmable cells, so in-circuit programming requires little external circuitry.

All these distinctions give SiliconBlue a shot at two markets in which FPGAs have been notably unsuccessful in the past, according to Shankar. The CEO notes that FPGAs are in fact already accepted in consumer electronics: for example, moderate-sized FPGAs have prospered as interconnect bridges and logic extenders in format converter boxes and high-definition TVs. But these are applications that are both tethered to a source of line power and relatively high-cost.

Handsets, in contrast, have been almost immune to the appeals of the FPGA. Both the cost and—primarily—the energy consumption over realistic use profiles have made the handset unfriendly to even small PLDs used as glue logic, and outright hostile to FPGAs large enough to implement significant hunks of system core logic.

Shankar believes the SiliconBlue combination of logic density up to about 8000 logic cells, the previously stated low dynamic and static power, and high-volume unit cost in the few-dollars range, augmented by the advantage of no external ROM, will break open this barrier. He sees the parts finding use in the more expensive smartphones, both as application accelerators to ease the load on the applications CPU and to reduce energy for compute-intensive tasks, and as companion chips to the central SOC to provide product line flexibility and bug fixes.

If there is an obvious weakness to this story it is applications support. SiliconBlue has just over 20 employees in the USA, another dozen in China, and some contract relationships with other design teams. That has not left a lot of resources for tool or intellectual-property development. Accordingly, the company uses a Magma Design Automation front end tool chain, including Magma's timing-driven placement, coupled to a proprietary SiliconBlue router.

The difficult part of the story comes in the IP area. SiliconBlue currently offers about 30 elements in its IP libraly. Denny Steele, director of marketing and applications, says that the library comprises three sections. The first section is more in the way of design examples: "how to do this in our parts," he describes it. The second section contains application-specific designs such as voltage translator blocks. The third section includes major functional blocks such as a graphics controller. So far, as SiliconBlue has explored applications with its initial prospects, the latter blocks are necessarily based on customer request.

With a strong foundry relationship, proven interest from handset designers, and a roadmap to TSMC 40 nm, the company has a solid technical foundation. Shankar says SiliconBlue is sampling parts from its first family now. What happens next may depend both on the small company's ability to execute on a good idea, and on the response of the well-entrenched rest of the FPGA community, where an attempt to open the handset market to FPGAs will not go unnoticed.

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