- Practical Chip Design - Blog on EDN - 1690000169
Tuesday, August 5, 2008
There is a long-standing debate in the industry over the future of FPGAs. The FPGA vendors have argued for years that their destiny is to replace ASICs as the way most digital systems are implemented. And in fact ASIC design starts have been falling for several years, as FPGA design starts have continued to rise, although these two numbers actually mean quite different things, making even a relative comparison murky.
But skeptics have pointed out that FPGAs themselves are vulnerable to replacement. ASIC vendors argue that they have not been losing design starts to FPGAs—they have simply been moving up-market, into the large SoC and mixed-signal designs of which FPGAs are incapable, hampered as the FPGAs are by limited density and performance, relatively high power consumption, and lack—with the exception of one Actel family—of configurable analog blocks. The decline in ASIC design starts has been not so much from incursion of FPGAs, the skeptics say, as from the simple fact that as integration goes up, the number of design starts necessary to complete a system goes down. Not many products require more than one SoC to be designed any more, especially in the dominant consumer electronics industry.
The most frequent conclusion from all of this debate has been that FPGAs own the logic prototyping world, having all but completely displaced big-iron logic verification systems. They also own the low-gate-count, low- to moderate-volume digital IC world: the space once occupied by gate arrays, and briefly the focus of the Structured ASIC movement.
But In recent months, we are seeing more tangible signs that this well-defined homeland for FPGAs may be under threat. First, we have seen attempts at incursion on the turf of Altera and Xilinx by what was supposed to be unthinkable: an FPGA start-up, SiliconBlue. The SiliconBlue product is still very much a conventional, SRAM-programmed FPGA, but the fact that a start-up could be funded and launched against such a mature industry infrastructure in itself implies cracks in the foundations.
The next indication came from what was supposed to be a moribund effort: the Structured ASIC world. This week Structured ASIC pioneer eASIC announced that not only did it have 120 design wins for its 90 nm product line, but that it was already working on customer designs for a 45 nm product family. The company's strategy not only cuts a swath across the sweet spot of the FPGA business—high-value, low- to moderate-volume SoCs—but it cuts into the conventional cell-based ASIC space as well. [Disclaimer here: the author has a small financial interest in eASIC, so be properly skeptical.]
It is not surprising that the Structured ASIC world is fighting back. The value proposition of the concept—an ASIC built on a pre-manufactured logic and memory array that could be configured using a few metal or via masks—was supposed to get better with each advancing process node, as cell-based design became harder and FPGAs fell further and further behind in power dissipation and system performance. In fact, based on eASIC's published numbers, that appears to be happening. Don't be at all surprised to see other vendors unveil structured products at 40 or 32 nm in the next couple of years. One interesting speculation: this could be a very interesting business proposition for a company with both foundry and IP assets and strong relationships in the fabless semiconductor industry, where many of the potential customers for such products are--someone like, say, a TSMC.
But wait, there's more. In a recent press event, Pierre-Yves Lesaicherre, senior vice president and general manager at NXP Semiconductor, made some very interesting remarks about the microcontroller market. Yes, microcontrollers—you know, the little 35-cent parts in ancient technology that run toasters? Think again.
Goeff Lees, vice president and general manager of the microcontroller product line at NXP, pointed out that far from being sponges for legacy fab capacity, 32-bit MCUs are closing in on the leading edge of process technology. "It's been a while since we designed a 32-bit microcontroller to run in a mature process, and that's a big change in strategy. A few years ago the MCU market was three years behind Intel's best production process technology. Now we are nine months behind," Lees said.
So what? Well, 32-bit microcontrollers, especially multi-core designs with sophisticated peripherals, are in many ways highly flexible ASSPs. That is really a more accurate characterization than to call them MCUs in anything but a purely architectural sense. As such, they can complete against ASSPs from fabless semiconductor vendors. But they can also compete against FPGAs, offering lower design time, higher performance, much better power consumption, and much lower price for large designs. In many ways, an application-targeted MCU is a reference design in silicon—almost literally to the point where all you do is modify a few software modules to differentiate your product.
And that is exactly what is happening, according to Lesaicherre. "Our microcontrollers have been eating into the bottom of the CPLD and FPGA markets," he said. As the computing power and memory on the dice improves—as it inevitably will, with 65 nm and 45 nm parts in design today—that appetite will extend to the heart of the FPGA market as well. The microcontrollers will be able to target a range of similar applications with a 32-bit processor cluster, a well-chosen accelerator or two, and a good set of peripherals. The compute-intensive, mostly standards-based tasks will go to the accelerators, and the differentiating features will go into software on the ARM cores.
It is a threat to both the FPGA and ASIC worlds—not just because it threatens to divert some design starts, but because—like the Structured ASIC threat—it attacks the heart of the FPGA business model. The big FPGA guys don't make their real money selling prototyping chips for $2,500 a piece. They make their money landing a design win for a medium-sized FPGA in early production, and then sticking in there as the product goes to moderate volumes—or in the case of Altera, shifting the volume to HardCopy as demand builds. And it is those moderately-complex, processor-based, few-million-gate SoCs in moderate volumes that will be most under threat from the alternatives. That is especially true for the MCU threat, since modern MCUs bristle with high-quality data-converters, giving them the analog functionality that FPGAs and Structured ASICs conspicuously lack.
This is not to say that any FPGA vendor is doomed. Nothing with momentum dies over night, and FPGAs still offer a strong value proposition in many areas—especially if the application allows the sort of cut'n'try design style for which the reprogrammable parts are beloved. None the less, it's going to be an interesting couple of years for the FPGA business.
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Practical Chip Design
EDN Executive Editor Ron Wilson explores how IC design teams really work: the struggle for power efficiency and performance, wrestling with semiconductor processes and design methodologies, the challenges of global design teams. How do we somehow herd architecture, IP, design and verification into a successful tape-out?
- 출처: http://www.edn.com/blog/1690000169/post/190031219.html?nid=2435&rid=228590015
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