2006년 7월 13일 목요일

프로그래머블 로직 디바이스, FPGA 디자인 보안

프로그래머블 로직 디바이스

by 글: 지 펭(Jie Feng), 알테라 코퍼레이션
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http://www.ecnkoreamag.com/article.asp?id=5351

오늘날 디자인의 복잡성이 증가함에 따라서 FPGA 디자인 보안의 중요성이 갈수록 높아지고 있다. 밀도, 기능성, 성능이 높아지고 있는 FPGA는 낮은 개발 위험성, 신속한 출시시간, 개발 유연성에 대한 시장 요구사항에 따라, 주요 시스템에서 점차 ASIC을 대체하고 있다. 첨단 기술을 제공하는 FPGA가 다양한 제품에 탑재되고 있는 가운데, IP(지적재산) 도용은 기업들에게 중요한 문제가 되었다.

어느 정도의 진전은 이루어지고 있으나 전세계적으로 적용할 수 있는 IP 법규는 없다. 그러므로 설계 엔지니어들이 FPGA로 구현된 디자인을 보호함으로써 IP, 수익성, 경쟁 이점을 적극적으로 보호해야 한다. 군사 분야에서는 각국이 군사 시스템을 개발하고 이전하기 위해 동맹국 간에 협력을 장려하고 있다. 해외로 판매되는 군사 시스템의 수가 증가함에 따라 군사 기술 및 정보를 보호해야 할 필요성도 높아지고 있다.

FPGA 디자인 보안 기법

FPGA는 크게 휘발성과 비휘발성의 두 가지 유형이 있다. 휘발성 FPGA가 비휘발성 FPGA에 비해 밀도와 기능성이 높고 가격이 낮다. 하지만 휘발성 FPGA는 SRAM 기반으로서 전원이 꺼졌을 때 데이터를 잃는다. 데이터를 저장하기 위해서는 외부 메모리가 필요한데 이것이 보안 위험성을 야기한다. 비휘발성 FPGA는 전원이 꺼졌을 때 프로그래밍 데이터를 유지하므로 외부 메모리 디바이스가 필요하지 않다.

현재 휘발성 FPGA의 디자인을 보호하기 위해서 컨피규레이션 비트스트림 암호화 및 핸드세이킹 토큰의 두 가지 기법이 이용되고 있다. 한편, 비휘발성 FPGA는 보안 비트를 이용해서 디자인을 보호한다.

휘발성 FPGA에 컨피규레이션 비트스트림 암호화 이용

최근의 일부 휘발성 FPGA는 컨피규레이션 비트스트림 암호화를 위해 빌트인 암호해독 엔진과 주요 스토리지를 포함한다. 그림 1은 3단계로 이루어지는 보안 컨피규레이션 흐름을 보여준다.

1. FPGA로 보안 키를 로드한다.
2. 이 키로 컨피규레이션 파일을 암호화하고 컨피규레이션 메모리 또는 플래시 메모리 등의 외부 메모리에 저장한다.
3. 시스템 파워업 때 외부 메모리가 암호화된 컨피규레이션 파일을 FPGA로 전송하면 FPGA가 저장된 키를 이용해 실시간으로 컨피규레이션 파일을 해독하고 스스로를 컨피규레이션한다.

컨피규레이션 데이터를 암호화하고 해독하기 위해서는 AES(Advanced Encryption Standard) 등의 산업표준 암호화 알고리즘이 이용된다. 보안 키 저장은 FPGA에 따라 휘발성 또는 비휘발성으로 나뉜다. 휘발성 키 저장의 경우에는 파워다운 때 외부 백업 배터리가 필요하다. 배터리는 사용시간이 제한적이고 동작 환경의 영향을 받으므로 유지관리 비용이 증가한다. 또한 배터리의 화학적 성분 때문에 특정 애플리케이션에는 적합하지 않다. 비휘발성 키 저장이 디바이스를 보드에 탑재 또는 탑재하지 않고 제조 공정의 어느 단계에서나 FPGA로 키를 프로그램할 수 있으므로 훨씬 더 믿을 수 있고 유연하다.

컨피규레이션 비트스트림 암호화를 이용하면 암호화된 컨피규레이션 파일만 시스템에 설치되고 키는 FPGA에 저장된다. 그러므로 컨피규레이션 비트스트림이 포착되더라도 키가 없으면 해독할 수 없다. FPGA 안의 보안 키를 은폐하기 위해 여러 가지 방법이 이용된다. 한 가지 방법이 금속층 아래에 분산적으로 배치하는 것이다. 알테라를 포함한 일부 업체에서는 추가적인 보안 기법을 이용해서 키를 더 찾기 어렵게 만든다.

휘발성 FPGA에 핸드세이킹 토큰 기법 이용

컨피규레이션 비트스트림 암호화는 대다수 저비용 FPGA에는 이용할 수 없다. 핸드세이킹 토큰 기법이 어느 FPGA 디자인에서나 컨피규레이션 비트스트림을 포착하더라도 복제를 방지할 수 있는 기법이다. 이 기법은 안전한 외부 디바이스로부터 FPGA로 핸드세이킹 토큰이 전달될 때까지 FPGA 안의 사용자 디자인의 기능을 정지시키는 것이다. 안전한 외부 디바이스가 FPGA로 연속적인 핸드세이킹 토큰을 발생시켜서 연속 동작을 가능하게 한다. 이는 그림 2의 소프트웨어 라이선스 기법과 유사하다.

이 예에서는 안전한 외부 디바이스로 CPLD를 이용했다. CPLD로부터의 핸드세이킹 토큰과 FPGA에서 생성된 데이터가 일치할 때만 FPGA 사용자 디자인이 동작한다. 그러므로 사용권이 없는 소프트웨어와 마찬가지로 FPGA 컨피규레이션 비트스트림을 훔치더라도 이것이 쓸모가 없다.

비휘발성 FPGA에 보안 비트 이용

비휘발성 FPGA는 크게 플래시, 앤티퓨즈, 온칩 컨피규레이션 메모리를 이용한 SRAM의 세 가지 유형이 있을 수 있다. 비휘발성 FPGA는 시스템 셧다운 때 자신의 컨피규레이션을 유지한다. 플래시 FPGA와 온칩 컨피규레이션 메모리를 이용한 SRAM FPGA만 재프로그래밍이 가능하다. 앤티퓨즈 FPGA는 재프로그래밍이 불가능하므로 유연성이 떨어진다.

대부분의 비휘발성 FPGA가 컨피규레이션 파일 리드백 또는 프로빙을 지원하므로 디버그 및 테스트에는 용이하지만, 잠재적인 보안 위험성에 노출되어 있다. 이를 방지하기 위해 이들 FPGA는 보통 리드백 기능을 켜거나 끌 수 있는 보안 비트를 가지고 있다. 이들 FPGA의 보안성은 이 보안 비트가 얼마나 잘 보호되느냐에 따라 좌우된다.

애플리케이션에 따라 적합한 FPGA 선택

대부분의 애플리케이션에서 신뢰성이 중요하므로 비휘발성 키를 이용한 휘발성 FPGA나 비휘발성 FPGA가 IP를 보호하는 데에는 더 유리하다. ASSP나 FPGA를 통해 제공되는 IP 등의 애플리케이션에는 비휘발성 키를 이용한 휘발성 FPGA나 비휘발성 FPGA가 외부 배터리가 필요하지 않으므로 적합한 선택이라고 볼 수 있다.

군사 애플리케이션의 경우에는 높은 수준의 보안이 요구된다. 그러므로 FPGA 디자인 보안은 전반적인 프로세스의 일부에 불과하다. 따라서 전체 군사 시스템의 보안을 위해서는 다른 보안 수단을 추가해야 한다. FPGA를 선택할 때는 디바이스 밀도, 성능, 기능, 비용 등 그 밖의 요인들을 고려해야 한다. 컨피규레이션 비트스트림 암호화 및 핸드세이킹 토큰 보안을 이용함으로써 디자이너가 고밀도 저비용 FPGA의 풍부한 기능셋을 이용해서 IP를 보호할 수 있다.

저자 소개

지 펭은 알테라의 스트라틱스 시리즈 FPGA 제품 총괄 책임자이다. 알테라에서 6년 동안 재직했으며 가전 애플리케이션, 무선 기술 마케팅, 제품 마케팅을 담당했다. 다수의 잡지 및 일간지와 다수의 컨퍼런스에서 FPGA 디자인 보안에 관한 글을 기고하거나 발표했다. 토론토대학에서 컴퓨터공학을 전공했으며 스탠포드대학에서 컴퓨터과학으로 석사학위를 취득했다. 더 자세한 사항은 www.altera.com 참조하기 바란다.

2006년 7월 11일 화요일

자동으로 전원 차단하는 CPLD

자동으로 전원 차단하는 CPLD

by 라파엘 카마로타(Rafael Camarota), 알테라 코퍼레이션
http://www.ednkorea.com/article.asp?articleid=2992 - EDN Asia

요즘 나온 대부분의 CPLD(complex programmable-logic devices)가 절전모드를 갖추고 있다고는 하지만, 시스템이 작동하지 않을 때 완전한 시스템의 중단으로 배터리 에너지 보존을 극대화하는 방법을 설계 엔지어들은 모색하고 있다. 그림 1은 CPLD에 개별 부품들을 추가하는 방법으로 배터리 구동 시스템의 전원차단 회로를 구현하는 방법을 소개한다. 이 회로에는 알테라의 EPM570-T100이 사용됐다. 외부 P 채널 MOSFET인 Q1에는 인터내셔널렉티파이어(www.irf.com)의 IRLML6302 또는 동급 제품이 사용됐다. Q1은 CPLD인 IC1과 시스템의 다른 부품들을 위해 전력을 제어하는 스위치 역할을 한다. CPLD와 스위치들의 배열은 MOSFET의 게이트를 제어하는데, 이는 사용자가 스위치를 누를 때마다 Q1의 스위치를 온(on)시키는 바이어스를 적용함으로써 구현된다. CPLD에는 스위치와 시스템 활동을 모니터링하는 임베디드 타이머가 포함돼 있어, 지정된 비활동 시간이 지나면 이 타이머는 MOSFET의 게이트 구동을 비활성화시키고, CPLD와 기타 MOSFET에 연결된 부품들에 공급되는 전력을 차단한다.

Q1의 소스는 배터리의 양극 단자에 연결된다. 드레인은 IC1의 VCC(INT), VCC(IO1), VCC(IO2) 전력 핀과 전원 차단 제어를 필요로 하는 다른 부품들에 연결된다. 전원 스위치가 오프되면 1kΩ 풀업저항인 R3이 0V 게이트-소스 전압으로 게이트를 유지함으로써 Q1을 오프 상태로 유지한다. IC1을 오프시키면, IC1은 CPLD의 전원차단 핀을 통해 접지에 누설 경로를 제공한다. EPM570-T100은 핫소켓 보호 기능을 포함하고 있는데, 이 기능은 사용자가 접근할 수 있는 디바이스 I/O 핀의 가용 전류를 300μA 미만으로 제한하는 역할을 한다. 따라서 최악의 경우일지라도 I/O 핀이 R3을 통과해 생성하는 전압은, FET의 최소 게이트 임계 턴온 전압인 0.7V에 도달하지 않는다.

아무 스위치나 누르면 스위치의 접점과 이에 연결된 다이오드를 통과하는 전류 경로가 생성된다. 이후 R3을 거쳐 약 2.3V의 게이트 소스 바이어스가 생성된다. 이는 100μsec 동안에 Q1을 온시키고 IC1을 동작시키기에는 충분하다. 기계식 스위치를 작동시키면 온타임이 적어도 3msec 정도가 되지만, 보통 사람들의 수조작에 의한 눌렀다 떼기 동작에는 최소 30msec이 소요된다. 상대적으로 느린 이러한 응답시간 동안에 CPLD는 온 상태가 될 수 있지만, 내부 회로를 리셋하고 전원차단 핀을 로직 제로로 가정함으로써 조작자가 누른 스위치를 떼기 전에 Q1을 온시킬 수 있다.

사용자가 지정한 애플리케이션 로직 외에 이 CPLD의 전력제어 로직은 한 쌍의 표준 파라미터의 라이브러리 매크로 회로를 추가한다. 이 회로는 알테라(www.altera.com)의 Quarus II 개발 툴에 의해 생성된다. 내부 4.4MHz±25% 오실레이터인 Altufm_osc는 modulo-44-million LPM(library-parameterized-module) 카운터를 구동한다. 이 카운터는 CPLD의 애플리케이션 로직이 생성하는 로직 로우 신호 또는 스위치 닫기에 의해 리셋된다. 카운터를 리셋하면 캐리아웃(carry-out) 신호가 낮아지고, 외부 전원차단 핀이 구동된다. 사용자가 리셋을 제거하면 반전된 캐리아웃 신호는 LPM 카운터를 재활성화한다.

모든 스위치를 열어 두고 애플리케이션 로직이 비활성 상태가 되면 카운터는 약 10초 안에 4,400만까지 계산하며, 내부 캐리아웃 신호가 상승하면서 카운터를 비활성화하고 캐리아웃 신호를 높은 상태로 유지한다. 그 다음 전원차단 핀이 VCC를 향해 올라가면서 전력차단 핀의 전압이 2.3V에 이르면 Q1을 오프시킨다. CPLD에서 전력을 제거하면 전원차단 핀이 트라이스테이트(tristate) 또는 연결해제 모드가 되며, R3이 Q1을 오프 상태로 유지히게 된다.

설계 엔지니어는 JTAG 호환 명령을 사용함으로써 다운로드 케이블과 함께 EPM570-T100을 구성할 수 있다. 이 케이블은 제조업체가 정의한 10핀 헤더에 연결될 수 있다. 이 과정에서는 구성 전, 구성 중간, 구성 후에 외부 스위치를 눌러 CPLD가 모든 구성 과정에서 전력을 공급 받도록 해야 한다. 카운터의 계수를 바꾸면 모든 필요한 값으로 비활성 타임아웃을 설정할 수 있다. 전력, 접지, JTAG 신호는 특정 디바이스 핀을 사용하지만, 어떤 범용 CPLD I/O 핀이라도 스위치용 입력과 전원차단 출력으로 할당될 수 있다.

설계 엔지니어의 애플리케이션에 푸시버튼 스위치 매트릭스가 필요한 경우에는 n 다이오드를 사용함으로써 효율적인 파워업(power-up) 감지에 활용되는 nxm 스위치 매트릭스를 구성할 수 있다(그림 2). 이 예에서 다이오드 D1에서 D4까지 MOSFET의 게이트에 스위치 행이 연결된다. 저항 R8~R11은 각 스위치 열에 대한 접지 경로를 제공하고, 키가 닫히는 동안에만 전류를 전달한다. 또한 파워 서플라이 전류 드레인을 최소화하기 위해 대기하는 동안 열(column) 입력을 낮게 유지한다.

사용자가 아무 키를 누르면 Q1의 게이트가 낮아져 CPLD를 온시킨다. 빠른 CPLD 전원 인가 루틴을 통해, 이 애플리케이션은 사용자가 누른 스위치를 떼기 전에 스위치 매트릭스의 행과 열을 검색하고 사용자가 어느 스위치를 눌렀는지 확인할 수 있다. 이 애플리케이션에서 행 신호는 LPM 카운터의 비활성 타이머를 리셋한다.

2006년 7월 7일 금요일

음성 부호화 기술

음성 부호화 기술

가. 개요

  • 사람의 음성 주파수는 70~7000Hz의 대역을 가지지만, 요해도를 해치지 않는 300~3400Hz를 음성대역으로하고, 보호대역 감안하여 8KHz로 표본화함.
  • 음성신호를 디지털 신호로 부호화하는 방법에는 파형 부호화, 음원 부호화, 혼합부호화 방식이 있으며,
  • 주요 기술은 PCM, ADPCM, SB-ADPCM, LD-CELP, CS-ACELP등이 있음.

나. PCM (G.711)

  • G.711은 64Kbps PCM 기술을 이용한 음성부호화 방식의 표준이며, 1972년 ITU-T에 의해 권고됨.
  • 파형 부호화 방식의 하나로, 아날로그 음성신호를 표본화, 양자화, 부호화하여 디지털로
    전송하고, 수신측에서 복호화함으로써 아날로그 음성신호를 재생시키는 방식임.
  • 양자화 잡음을 줄이기 위해 양자화 전에 압축하고, 복호화 후 신장하는 비선형 양자화
    기법을 사용하는데, 북미 μ-Law 방식과 유럽 A-Law 방식이 있음.

다. ADPCM (G.721)

  • G.721은 32Kbps ADPCM 기술을 이용한 음성부호화 및 압축방식의 표준이며, 1984년 ITU-T에 의해 권고됨.
  • ADPCM은 음성신호의 시간 상관성이 큰 특성을 이용하여 입력신호와 예측 값과의 차이를 4비트 양자화 함으로써 전송 비트율을 감소시킴.
  • 적응 양자화기, 적응 예측기를 사용하여 PCM과 거의 동등한 음질을 얻음.

라. SB- ADPCM (G.722)

  • Sub-Band ADPCM은 고품질의 현장감있는 음성통신을 위해 50Hz~7KHz 광대역을 64Kbps 이하의 고품질로 부호화하는 기술로서 1986년 ITU-T에 의해 G.722로 권고됨.
  • 디지털 필터에 의해 저역(0~4 KHz)과 고역 (4~8kHz)으로 분할하여 처리 (ADPCM)한 후 다중화시켜 전송 (64kbps로) 함.
  • 음성 회의를 보완하는 멀티미디어 통신회의에 응용함.

마. LD-CELP (G.728)

  • G.728은, 저속의 이동 통신을 위해 16Kbps로 부호화하면서도 G.721과 동등이상의 음질을 얻을 수 있다.
  • LD-CELP (Low Delay - Code Excited Linear Prediction) 기술을 이용한 음성 부호화의 표준이며, 1992년 ITU-T에 의해 권고 됨.
  • 인간의 청각 특성을 고려, 음성신호의 5샘플을 1 프레임으로 하는 10바이트만 전송함으로써 부호화 지연 2ms내에서 높은 음질을 구현함 (벡터 단위처리)

바. CS-ACELP (G.729)

  • Conjugate Structure - Algebraic Code Excited Linear Prediction
  • 8kbps 로 G.721 보다 음질이 좋음.

사. (G.723.1) MP-MLQ (Multi Pulse - Mucti Level Quantization)

  • 6.3 Kbps로 G.721 보다 음질이 좋음.
  • 5.3 Kbps ACELP 방식도 있으나 음질은 떨어짐.

아. 상호 비교

표준

압축방식

속도

MOS

응용

G.711

PCM

64 Kbps

4.1

전화국간 디지털 전송

G.721

ADPCM

32 Kbps

3.85

가정 또는 기업의 CODEC

G.722

SB-ADPCM

64 Kbps

(오디오신호)

멀티미디어 음성회의. AM 방송 품질

G.728

LD-CELP

16 Kbps

3.61

디지털 이동통신, ISDN, FR망 음성용

G.729

CS-ACELP

8 Kbps

3.92

H.323, H.320 영상회의 단말.
이동통신, FR망 음성용

G.723.1

MP-MLQ

6.3 Kbps

3.9

이동통신, H.324 등 영상회의 단말
VOIP 포럼 추천

ACELP

5.3 Kbps

3.65

2006년 6월 26일 월요일

흥을 깨는 사람들

제목이 좀 재미있을런지...?
이런내용의 글들은 여기저기서 단편적으로 많이들 보셨을것 같은데요...

누군가 고마우신 분께서 한곳에 모아두셔서 제가 퍼왔습니다...

지금은 당연시 여기는 여러 생각들이 발명당시에는 어찌도 이렇게 황당한 취급을 받았는지 정말 웃기기만 합니다... 기존의 고정관념과 새로운 생각사이에는 이렇게 어찌해볼 수 없을 만큼 커다란 장벽이 있는가 봅니다...

Thanks... C.W. :)



흥을 깨는 사람들

"이 전화기는 단점이 너무 많아 통신 수단으로 고려할 가치가 없을 뿐 아니라 우리에게 아무 소용도 없는 물건이다."
- 벨이 개발한 전화에 대한 웨스턴 유니온의 메모(1876년)

"발상도 흥미진진하고 구성도 좋다. 하지만 C학점이상 받으려면 실현 가능성이 있어야 한다."
- 익일 배송 서비스(Overnight delivery service)를 연구한 프레드 스미스의 논문에 대한 한 예일대학 경영학과 교수의 답변. 스미스는 후에 페덱스를 설립했다.

"재고할 가치가 없으니 우리에게 굳이 신발 제조법에 대해 이야기하지 말라."
- 대형 신발 제조 업체가 나이키 런닝 슈즈의 걸작이라고 여겨지는 '와플(Waffle)" 개발자이자 나이키의 공동 창업자인 빌 바워만에게 한 말.

"그래서 저희는 아타리(Atari) 사를 찾아가 '귀사의 일부 부품을 사용하기는 했지만 정말 멋진 제품을 개발했습니다. 저희에게 자금을 대주실 수 있습니까? 아니면 저희가 이 제품 개발 노하우를 제공할 수도 있습니다. 저희가 바라는 것은 이 제품이 세상에 나오는 것뿐입니다. 월급만 준다면 귀사를 위해 일해 보겠습니다.'라고 했지요. 그러니까 그 친구들, '그렇게는 안 된다'고 하더군요. 그래서 할 수 없이 휴렛패커드를 찾아 갔더니, '당신들은 필요 없어. 아직 대학도 졸업 못했잖아'라고 거들떠 보지도 않더라고요."
- 워즈니악(Wozniak)과 공동 개발한 PC로 아타리와 휴렛패커드의 관심을 끌어 보려고 했던 것에 대해 스티브 잡스가 한 말. 잡스와 워즈니악은 후에 공동으로 애플컴퓨터 사를 창업했다.

"'그것들을 가맹점화해야 합니다. 제가 여러분의 실험 대상이 되겠습니다.'라고 제가 간곡하게 말했지만 그들은 콧방귀도 뀌지 않았습니다! 그들에게서 경영 철학을 볼 수 없었어요. 우리의 제안을 거절하자 버드와 저는 독립했습니다."
- 샘 월트는 1962년 할인 소매 아이디어에 관심이 있어 벤 플랭클린 체인을 사려고 노력했던 때를 상기하면서 이렇게 말했다. 월튼은 후에 월마트를 창업했다.

"배우가 말하는 것을 듣고 싶어 하는 사람이 어디 있다고 그래?"
- 워너 브라더스의 워너가 최초의 유성 영화 제작을 거부하며 한말(1927년).

"음향이나 기타 치는 소리나 마음에 드는 게 하나도 없어!"
- 비틀즈 음반 취입을 거부하며, 데카 레코드(1962년).

1884년, 존 헨리 패터슨은 금전 등록기에 대한 권리를 획득하기 위해 동업하는 친구에게 6,500달러를 빌려 달라고 했다거 조롱만 당했다. 패터슨은 후에 NCR(National Cash Register, 최초의 금전 등록기 개발 회사)을 창업했다.

"의학에 컴퓨터를 이용하려 하다니 정말 정신이 나간 친구군. 나는 컴퓨터에 자신도 없고 그것으로 아무것도 하고 싶지 않소."
- 영국의 의학 교수가 CT 스캐너에 대해 존 알프레드 파웰에게 한 말.

"석유를 캔디고? 땅을 파서 석유를 캐내? 그런 엉터리 같은 생각을 하다니!"
- 채굴 경험이 풍부한 사람이 1859년 석유 시추를 하려는 에드윈 드레이크에게 한 말. 그레이크는 후에 최초의 석유 시추 개발업자가 되었다.

"비행기는 재미있는 장난감일 뿐 군사적인 가치는 전혀 없다."
- 제1차 세계대전 당시 연합군의 서부 전선 최일선에서, 페르디앙 포슈(프랑스 육군원수, 1911년).

"어두컴컴한 실내에서 지속적으로 보아야 하기 때문에 텔레비전은 결코 대중들 사이로 파고들지 못할 것이다."
- 하버드 대학교수, 체스터 도즈.

2006년 6월 23일 금요일

벌써 일년...

"브라운아이즈"의 노래 제목이 아니다...
이곳 blog를 open한지도 벌써 1년이 되었다...
처음 시작때의 마음가짐과는 달리 좀 이상해져 가는것 같아 못내 아쉽다...
아직까지는 잘 하고 있는 짓이라고 생각하며 지내고 있긴한데...
Um~~~ 글쎄~~~

2006년 6월 21일 수요일

Radiospire applies WiMAX to uncompressed HDTV

 
Radiospire applies WiMAX to uncompressed HDTV

The brewing battle for the fast home digital media network is mainly focused on Wi-Fi and the UltraWideBand technologies, with a couple of left field candidates such as 60GHz (see separate item). Another of these contenders is start-up Radiospire Networks, which is creating chips for in-home WiMAX networks optimized to stream high definition television.

Radiospire claims to retain wired image quality with its high definition multimedia interface (HDMI) chipset, which enables wireless HDTV connectivity without compressing the video signal. The technology supports 720p, 1080i and 1080p HDTV formats with industry-standard HDCP encryption. Radiospire says compression-based wireless products, such as those based on WiMedia UWB or 802.11n fast Wi-Fi, present encryption challenges that limit their ability to handle copy protected content. Throughput is up to 3Gbps for 1080p formats.

“Wireless home theater connectivity is becoming a necessity, but until now the solutions available have had major drawbacks because of the use of compression,” said Tandhoni Rao, CEO of Radiospire.

The new chipset solution consists of a SiGe RF transceiver chip, ADC/DAC, and a CMOS baseband device. It operates in the 3.1-4.8GHz range to avoid interference with Wi-Fi and other signals in 2.4GHz and 5GHz. The 720p/1080i configuration is sampling now with 1080p to follow in the second half of the year.

Another company focused on indoor applications of WiMAX is chip designer Cygnus Communications, which last year demonstrated a software defined platform for 802.16 at the SuperComm show, designed to compete with fast Wi-Fi.

In a 5GHz Lan environment, many of WiMAX’ characteristics will be similar to those of the OFDM-based variants of Wi-Fi, such as 802.11a and future releases. However, over LAN distances it will boast higher data rates than ‘a’, though not necessarily than the upcoming 802.11n, which could reach several hundred Mbps in its second generation.

The main attraction in unlicensed spectrum will be its quality of service mechanisms, which Cygnus believes are far better than those of the planned QoS extension to the 802.11 standard, called 802.11e, or the interim solution proposed by the Wi-Fi Alliance, WMM.

And then, WiMAX has the licensed spectrum options too, and so could offer a solution to spectrum holding service providers - as they start to bundle indoor media LAN facilities with other broadband offerings - that they could control.

Enhanced QoS will be important for streaming video around the home and to multiple devices such as televisions, laptops and handsets. An operator could use licensed WiMAX to deliver access and in-building LANs, by bundling a low power base station suited to indoor use with the normal WiMAX receiver.

2006년 6월 13일 화요일

Emailing: Display Resolution



   Display resolution

Wikipedia
Advertiser links
  The display resolution of a digital television or computer display is the number of pixels (or maximal image resolution) that can be displayed on the screen, usually given as a product of the number of columns (horizontal, "X") and lines (vertical, "Y"). The horizontal number is always stated first.

For analog TV sets, the horizontal resolution is related to the bandwidth of the luminance signal, and is stated in "lines", as the largest number of alternating vertical black and white stripes that can be displayed across the width of the picture without them merging together. Sometimes, the lines are counted across a width equal to the height of the picture, rather than across the full width of the picture. This gives rise to two different measures of horizontal resolution, which can lead to confusion. The vertical resolution, as with digital displays, is the number of horizontal lines in the picture.

Currently, common computer display resolutions are 640×480 (VGA, Video Graphics Array), 800×600 (SVGA, Super VGA), and 1024×768 (XGA/XVGA, eXtended). Some computer users, especially CAD users and video game players, run their computers at 1600×1200 resolution (UXGA, Ultra-eXtended) or higher if they have the necessary equipment. When a computer display resolution is set that is too high for the display, some systems make the virtual screen scrollable over the physical screen. With digital television and HDTV, vertical resolutions of 720 or 1080 scan liness are typical.

The 640×480 resolution, introduced with the IBM PS/2 VGA and MCGA (multi-color) on-board graphics chips, was the standard resolution from 1990 to 1997, partly due to its ratio. 800×600 has been the standard resolution from 1998 to the present, but 1024×768 is fast becoming the new standard resolution, especially since it also satisfies the ratio. Many web sites and multimedia products are designed for 1024×768 resolution. Most of today's computer games released during the "128-bit video game era", such as SimCity 4, do not support 640×480 at all. Windows XP is designed to run at 800×600 minimum (although it is possible to run legacy aplications in 640x480 compatibility mode).

With 15" and 17" (381 mm and 432 mm) monitors, 1024×768 resolution is the standard, whereas with 19" (483 mm) monitors, 1280×1024 is the recommended standard. Good 21" (533 mm) monitors are usually capable of 1600×1200 resolution. There are also 24" (610 mm) widescreen monitors on the market, and those will often be able to display 1900+ pixels horizontally.

Computer Standard Resolution
CGA 320×200 (16:10)
EGA 640×350 (approx. 5:3)
QVGA 320×240 (4:3)
VGA 640×480 (4:3)
SVGA 800×600 (4:3)
XGA 1024×768 (4:3)
WXGA 1280×768 (15:9)
SXGA 1280×1024 (5:4)
SXGA+ 1400×1050 (4:3)
WSXGA 1600×1024 (approx. 15.6:10)
WSXGA+ 1680×1050 (16:10)
UXGA 1600×1200 (4:3)
WUXGA 1920×1200 (16:10)
QXGA 2048×1536 (4:3)
WQXGA 2560×1600 (16:10)
QSXGA 2560×2048 (4:3)
WQSXGA 3200×2048 (approx. 15.6:10)
QUXGA 3200×2400 (4:3)
WQUXGA 3840×2400 (16:10)
HSXGA 5120×4096 (5:4)
WHSXGA 6400×4096 (approx. 15.6:10)
HUXGA 6400×4800 (4:3)
WHUXGA 7680×4800 (16:10)
Analogue TV Standard Resolution
PAL 720×576
PAL VHS 320×576 (approx.)
NTSC 640×482
NTSC VHS 320×482 (approx.)
Digital TV Standard Resolution
NTSC (preferred format) 648×486
D-1 NTSC 720×486
D-1 NTSC (square pixels) 720×540
PAL 720×486
D-1 PAL 720×576
D-1 PAL (square pixels) 768×576
HDTV 1920×1080
Digital Film Standard Resolution
Academy standard 2048×1536
DVD 720×480
Laserdisc 560×360

See also: computer display standards

 

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Display resolution

2006년 6월 2일 금요일

Power Management DesignLine | How you can manage multiple voltages in portables

03/23, 2005

How you can manage multiple voltages in portables
 
 
 
The proliferation of low-voltage processor, DSP and FPGA applications has created a need for digitally programmable power management control functions to meet the increasingly stringent supply rail requirements and the rapid changes placed on the power chain. Since system supply requirements change rapidly, a new "platform solution" that can change to meet any type of system power supply requirement eases the designer's job. This can be achieved by specifying a power "block" that can be standardized over a wide variety of applications and then digitally configured to individual requirements.

Typically, DC-DC converters are specified to meet ±2% initial setpoint accuracy and 3% over input voltage, loading and temperature conditions until end of life. This is insufficient for performance, testing and reliability reasons. Device voltage levels for multi-voltage Processors, DSPs and ASICs have fallen to 0.9V and are approaching 0.6V, making system voltage tolerances tighter and necessitating a new way to keep these voltage levels within specifications. If these requirements are not followed, performance degradation, fault conditions such as bus contention or device latch-up can arise. This article describes the importance of accurate DC output voltage control and a method to actively control any standard adjustable DC-DC converter module, discrete DC-DC PWM controller or LDO over time and temperature. A reference design using a standard Point-of-load (POL) DC-DC converter footprint and discrete switching regulator is shown with extremely accurate ±0.2% output levels. The POL automatically adjusts supply output voltage levels under all DC load conditions with programmable supply voltage margining allowing in-system test and control. A programmable 9-channel power supply PWM controller design is shown exhibiting ±0.5% accuracy. It forms a complete portable power system under digital control allowing dynamic adjustment of output voltage levels.

The need for accuracy and programmability As processor supply levels drop, both input current and voltage accuracy requirements increase. For this reason, systems are migrating from isolated distributed power to non-isolated distributed power architectures using POL solutions to gain improved voltage regulation and control at the load (Figure 1). Isolated distributed power uses 2 or more -48V isolated step-down DC-DC converters, which then route separate lower voltage supplies across the board. In the point of load distributed architecture, the -48V powers a single isolated DC-DC converter to provide an intermediate bus voltage. This intermediate bus voltage then powers many non-isolated DC-DC converters or LDO's at the load as shown in Figure 1.

Necessary power management functions

Figure 1 -- An example card design with power management functions necessary in data communications systems. These functions include Hot Swap, Supply Cascading/Sequencing and Tracking, Environmental Monitoring and Reset Control. As component power requirements change, the power management device can be in-system programmed using the I2C bus. The power supply is bussed from a main power bus and down converted directly at the load.

This architecture is more desirable because components making up the heart of the line card require lower voltages and higher currents and regulating at the load reduces inaccuracies. Power Management controllers are included to turn on/off and continuously monitor the POL supplies. Providing power at the load gives superior regulation, transient response and avoids voltage drops across PCB traces. This is necessary because as voltage levels decrease, allowable supply variations around these levels also decrease. Devices now not only require specific power supply turn on sequencing, but they also run at 1V or lower levels. These tighter limits demand more accurate control especially under changing load conditions and temperature variations to maintain optimal performance. The power system must automatically adjust and also test the limits of each board to guarantee performance and reliability. A highly integrated and accurate power supply manager, monitor and sequencer can achieve this required performance.

Processors are being marketed with various operating frequencies. For example, a processor with an operating frequency of 300MHz and a processor from the same manufacturer with an operating frequency of 700MHz are not fundamentally different. In fact, the 300MHz processor is not designed to run at 300MHz, it simply failed to perform to specification at 700MHz. Any processor manufacturer's data sheet will show that the higher performing processors are the result of processors yielding over a more stringent power supply rating.

The tighter power supply tolerances dictated by the high performance processor manufacturers have placed a heavy burden on the system designer. Typically, a processor's power supply tolerance is ±2.5%, which is ±25mV for a 1V supply. This power supply tolerance needs to be maintained over the full operating temperature of the board. When these challenges are compounded with board layout issues such as voltage drops across the power traces, board designers can find themselves in a desperate situation with a looming deadline.

There are several factors that affect the accuracy of a power supply. Take for example the standard structure of the non-isolated DC-DC converter shown in Figure 2. The resistor divider created by R1 and R2 sets the output voltage of the converter by feedback to the error amplifier against the reference voltage. This feedback keeps the inverting input terminal of the error amplifier and therefore the output of the supply equal to the converter's reference voltage. Inaccuracies in resistors R1 and R2 will cause errors in the set point of the converters output voltage. Variations in these resistors over temperature will increase the cumulative error. Errors in the converter's reference voltage also causes inaccuracy of the output voltage. Board layout can also decrease the accuracy of the DC-DC converter. Improper placement of the converter's voltage sense lines can result in uncompensated power trace IR losses to the load point.

Active DC Output Control
Active DC Output Control (ADOCTM) is one method of accurately controlling the output of a DC-DC converter or LDO to achieve high accuracy power supply voltages. Active DC Output Control is a new approach to intelligent power management. Using ADOC a designer can control the output of DC-DC converters or LDOs to ±0.2% for applications involving high performance processors. ADOC controls the output of a converter by effectively adjusting the resistors that set the output voltage of either a DC-DC converter or adjustable LDO. An ADOC solution is typically connected to a DC-DC converter as shown in Figure 2. The ADOC circuit stores the desired output voltage as a digital 10-bit value in non-volatile memory. The ADOC circuitry monitors the converters output at the load. After significant filtering and signal conditioning, the converter's output is compared to an inexpensive reference voltage accurate to ±0.1%. A decision is then made to increase or decrease the control signal to adjust the converter's output to the desired voltage ±0.2%.

ADOC connection

Figure 2 " The ADOC connection to a standard DC-DC converter. The ADOC function Controls DC-DC Converters via the TRIM pin. The CTRIM_CAP and RTRIM component type and values are determined for optimal operation. The RTRIM resistor is not necessary for DC-DC converter modules employing an on-board Trim Resistor.

The Output voltage in Figure 2 is derived from the following equations:
Eq1...Equation 1

Eq2...Equation 2

Where: 0.3 = TRIM output saturation voltage
Equation 3

and Vnom = Nominal non-trimmed output voltage

One problem with attempting to control the output voltage of a power supply is the possibility of interfering with the power supply's feedback control loop. Using two control loops is inherently risky and sometimes results in system instability. ADOC, however, uses a system of nonlinear, inherently convergent control to maintain system stability when coupled with the converter's control loop. The control loop of a DC-DC converter is optimized for fast transient response. On the other hand, the goal of ADOC is to accurately control the DC or average level of the output voltage. For controlling the DC voltage level the ADOC control loop runs very slow at 500Hz whereas the converters control loop responds to frequencies in the tens to hundreds of kHz. This large separation of loop response alone however does not guarantee system stability. The ADOC control loop employs a nonlinear digital control element where the adjustment to the output is always of the same magnitude. This nonlinear control induces a very small ripple voltage on the converter's output voltage. For any noise in the system with a magnitude greater than this induced ripple the gain of the ADOC control loop is less than 1. For noise of magnitude less than the induced ripple the gain is greater than 1. This noise is amplified until its magnitude is greater than the induced ripple where the loop then has a gain of less than 1. This sequence is referred to as a stable limit cycle in nonlinear systems. The induced ripple can be set with the ADOC circuit to less than 100μVp-p thus rendering it negligible.

The ADOC circuit is superior to simply using higher accuracy components such as the feedback resistors and the voltage reference for several reasons. The ADOC circuit actively controls the power supply's output so changes in temperature that affect the components of the converter result in only the ultra-low temperature variation associated with the ADOC circuit itself. Also, through the use of non-volatile memory to set the output voltage, ADOC can be used to voltage margin a converter's output accurately. This margining is a common practice among board designers to determine the robustness of a design by subjecting the board to the various voltage ranges. Some products use voltage margining as a production test to ensure system reliability. A returned board from the field is costly. Given this, companies are fearful of having marginal components on their boards. This has resulted in mandates for voltage margin testing every board that is manufactured.

The mechanism of supply margining is the same as that of supply controlling: adjust and hold the DC value of the supply. So naturally, ADOC also benefits voltage margin testing. If a mandate is set to margin test boards to ±10% with supplies that are only accurate to ±4%, the results can be unpredictable. For instance, are the supplies being margined to ±6% or are they margined to ±14%? In the 6% case the reliability test is ineffective. In the 14% case, a class of boards could be subject to yield or failure loss and the false positives result in longer debug times. Using ADOC to margin voltages in these tests increases the confidence of the test because it is well known how close the testing is to the margin limits.

The margin function can also be used for performance enhancement or to digitally control brightness by adjusting white LED backlights or contrast on an LCD as well as volume levels in an audio circuit.

The converter may be an off-the shelf compact device, or may be a "roll your own" circuit residing on the system board. In either case, the Active DC Output Control function dramatically improves voltage accuracy by implementing closed-loop active control. This utilizes the DC-DC's Trim pin as shown in Figure 2 or an equivalent output voltage feedback adjustment "VADJ" or "FB" node in a user's custom circuit.

To prove the ADOC concept, a non-isolated power supply reference design is shown in Figure 3. It is a fully functional POL DC/DC converter board used to demonstrate the improvement of using a digitally programmable nonvolatile supply voltage marginer and ADOC controller. The reference design operates from a +3.3V to +5V input and includes a synchronous PWM DC-DC converter, n-channel MOSFETs, and high current inductor. A precision voltage reference internal to the ADOC integrated circuit permits the DC-DC converter to be trimmed to within a 0.2% tolerance. The power management device controls the voltage monitoring, margining and trimming of the DC-DC PWM buck controller. Voltage margining along with many other programmable features are performed through the I2C 2-wire bus and Windows GUI interface (Figure 4). The key details of the design are the 16A Output Current with internal VREF, extremely accurate (±0.2%) control automatically adjusts supply output voltage level under all DC load conditions. A wide Margin/ADOC range from 0.3V to VDD with 2 programmable general purpose monitor sensors -- UV and OV with FAULT Output Flag, monitoring status and 256 Byte EEPROM, programmable nominal, high and low trim/margin voltages.

PoL reference design
click to enlarge
Figure 3 -- POL reference design of a digitally programmable DC-DC converter module rated to 15A at 1.5V. The design achieves a ±0.2% accurate DC-DC converter module using standard adjustable PWM controller, external FETs and ADOC function. This same design can be embedded on the system board.

GUI for PoL design

Figure 4 -- Windows GUI used to program and control the POL Reference design. All voltage levels and triggers are programmable using a Windows GUI and a PC-compatible parallel port to I2C serial bus programmer. Power management design is simplified using non-volatile programmable functions, when power is removed all settings are remembered.

Supply control using a programmable PWM controller for portable or handheld systems
To further standardization, a programmable supply voltage sequencing platform provides advantages over fixed solutions. One advantage is that a programmable solution reduces risks over changing system requirements. With a programmable solution the sequencing order can be modified and sequenced channels can be changed by simply reprogramming the controller. This minimizes the potential for having to re-spin the board when the system requirements are not clearly understood. A programmable solution also gives the designer more confidence that the board will work the first time. If a problem is encountered, reprogramming can get past the problem and onto debugging and testing the board for its intended function. On a company wide basis, the programmable solution also allows for cross platform implementation where an existing design can be reused for a unique solution by simply reprogramming.

A fully programmable power supply with integrated PWM controllers that monitors, margins, and cascade sequences provides all the power management needed in a power system. To provide a complete system, 9 voltage outputs plus voltage reference, consisting of: four synchronous PWM "buck" step-down converters, three PWM "boost" step-up converters, one PWM "boost-buck" negative DC/DC converter, and an LDO.

Typical portable power management schematic

Figure 5 -- Typical portable power management schematic using a 9-channel, programmable DC/DC controller. This integrated supply controller/manager provides power-on/off control, cascade sequencing and output margining.

The power system is capable of power-on/off cascade sequencing where each channel can be assigned to one of 8 unique sequence positions. Supplies may also be individually powered on/off through an I2C command or by assertion of one of two enable pins. Cascade sequencing, unlike time based sequencing, uses feedback to ensure that each output is within specification before the next channel is enabled.

Each output voltage and the input voltage or battery is monitored for under-voltage and over-voltage conditions. In the event of a fault, all supplies may be sequenced down or immediately disabled. Multiple output status pins are provided to notify host processors or other supervisory circuits of system faults. An Undervoltage Lockout (UVLO) circuit ensures the controller will not power up until the input or battery voltage has reached a safe operating value. The UVLO function exhibits hysteresis, ensuring that noise on the supply rail does not inadvertently cause faults or otherwise compromise the control of the output supplies.

In the event of a system fault, all monitored supplies may trigger fault actions such as power-off, or forced-shutdown operations. Each supply output may also be turned off individually at any point using the I2C command or one of two programmable enable pins.

In portable applications powered from a main system battery the battery voltage is continuously monitored for under-voltage conditions. There are two under-voltage settings for the battery; both are user programmable and have a corresponding status output pin. When the first threshold level is reached, the POWER_FAIL pin is asserted and latched. When the second threshold level is reached on the main supply, the nBATT_FAULT pin is asserted.

Voltage margin control of all output voltages through an I2C command by at least ±10% of the nominal output voltage is included. Margining creates three pre-programmed voltage settings that each channel can be set to via an I2C command. Margining is ideal when used with a channel configured as an LED driver where margining provides three brightness settings. In addition, each output is slew rate limited by digital soft-start circuitry that is user programmable and requires no external components.

All programmable settings are stored in non-volatile registers and are easily accessed and modified over an industry standard I2C serial bus. For quick prototype development Summit offers an evaluation card and a Graphical User Interface (GUI).

Cascade sequencing waveform

Margin High-Low waveform

Figure 6 - Power-on Cascade sequencing and Margin High/Low Waveforms. The supply channels are cascade sequenced-on to nominal voltage, margined high or low and then cascade sequenced-off. Channels 1, 2, 3, 4 are first margined high and then channels 2 and 3 are margined low. Up to 8 PWM supplies are controlled. (Ch 1 (500mV/D) = 1.25V Buck (Yellow trace), Ch 2 (500mV/D) = 2.5V Buck (Blue trace), Ch 3 (2V/D) = -7.5V Inverting Buck-Boost (Purple trace), Ch 4 (2V/D) = 12V Boost (Purple trace))

Conclusion
New digitally programmable power supply controller provide I2C programmable output voltages, Power on and off sequencing, Individual channel enable control, Battery monitoring, UV and OV monitoring on PWM outputs, Margining and Slew rate control. Actively controlling DC output voltage levels to within ±0.2% under light or full load to meet stringent tolerance requirements of high performance components further extends reliable operation and margining supplies tests system performance goals as well as providing an easy way to adjust brightness and volume control. The integration of active accuracy control, programmable features and built-in flexibility allows the system designer to create a "platform solution" that can be easily modified via software without major hardware changes. Combined with re-programmability, this facilitates rapid design cycles and the proliferation from a base design to future generations of product.

About the Authors:
Tom DeLurio is director of applications engineering at Summit Microelectronics. He is responsible for supporting customer implementation of Summit devices, evaluation kit production and new product definition. Before joining Summit, Mr. DeLurio held applications engineering management positions at Impala Linear Corporation. He has also held positions at Micro Linear Corporation, Aspen/Cypress Semiconductor, NCR Corporation's ASIC division, Honeywell, and Signetics Corporation. Mr. DeLurio has authored numerous articles for industry publications. He holds a BSEE degree from Pennsylvania State University. tom_delurio@summitmicro.com

George Hall is Staff Applications Engineer at Summit Microelectronics. He is responsible for supporting customers using Summit devices, evaluation kit design and new product definition. Before joining Summit, Mr. Hall was an applications engineering at Monolithic Power Systems. He has also held positions at Micro Linear Corporation, Micrel Semiconductor, Raynet, Computer Products, and General Electric. Mr. Hall has authored numerous application notes and holds a patent in phase-locking switched-mode power supplies. ghall@summitmicro.com

2006년 4월 27일 목요일

All about FPGAs

Source: http://www.pldesignline.com/shared/article/showArticle.jhtml?articleId=183701630



March 21, 2006

All about FPGAs

An industry expert examines field-programmable gate arrays (FPGAs), including current and forthcoming architectures, technologies, and software tools.

By Bob Zeidman

This article examines field-programmable gate arrays (FPGAs) and their underlying architectures and technologies. We will also examine current and up-and-coming software tools that are designed to allow you to squeeze more functionality into these chips in less time, running at faster speeds, and using less power.

Introduction
The first section of this article deals with the internal architecture and characteristics of typical FPGA devices, allowing you to decide which particular device is right for your design. The next section examines new FPGA architectures being offered by various vendors. The final section looks at some new software tools to help you with your designs.

The basics of FPGAs
Field-programmable gate arrays (FPGAs) are so-called because they are structured very much like the now-obsolete "gate array" form of application specific integrated circuit (ASIC). In fact, FPGAs essentially killed the gate array ASIC business. In the not-so-distant past, FPGAs were marketed for primarily two uses: (a) for prototyping ASICs and (b) for use in systems to achieve time-to-market knowing that they would be replaced with an ASIC implementation at the earliest opportunity.

With regard to this latter point, FPGAs can be programmed on your desk top in minutes while ASICs require weeks to fabricate a new design. As FPGA speeds increased, power consumption decreased, and prices decreased, FPGAs began shipping in products without any intention of replacing them with equivalent ASICs. Of course FPGAs are still good at prototyping ASICs and they are still used that way.

FPGA architectures
Each FPGA vendor has its own FPGA architecture, but in general terms they are all a variation of that shown in Fig 1. The architecture consists of configurable logic blocks, configurable I/O blocks, and programmable interconnect. Also, there will be clock circuitry for driving the clock signals to each logic block. Additional logic resources such as ALUs, memory, and decoders may also be available. The three basic types of programmable elements for an FPGA are static RAM, anti-fuses, and flash EPROM.


1. Generic FPGA architecture.

Configurable Logic Blocks (CLBs): These blocks contain the logic for the FPGA. In the large-grain architecture used by all FPGA vendors today, these CLBs contain enough logic to create a small state machine as illustrated in Fig 2. The block contains RAM for creating arbitrary combinatorial logic functions, also known as lookup tables (LUTs). It also contains flip-flops for clocked storage elements, along with multiplexers in order to route the logic within the block and to and from external resources. The multiplexers also allow polarity selection and reset and clear input selection.


2. FPGA Configurable logic block (CLB) (courtesy of Xilinx).

Configurable I/O Blocks: A Configurable input/output (I/O) Block, as shown in Fig 3, is used to bring signals onto the chip and send them back off again. It consists of an input buffer and an output buffer with three-state and open collector output controls. Typically there are pull up resistors on the outputs and sometimes pull down resistors that can be used to terminate signals and buses without requiring discrete resistors external to the chip.

The polarity of the output can usually be programmed for active high or active low output, and often the slew rate of the output can be programmed for fast or slow rise and fall times. There are typically flip-flops on outputs so that clocked signals can be output directly to the pins without encountering significant delay, more easily meeting the setup time requirement for external devices. Similarly, flip-flops on the inputs reduce delay on a signal before reaching a flip-flop, thus reducing the hold time requirement of the FPGA.


3. FPGA Configurable I/O block (courtesy of Xilinx).

Programmable Interconnect: In Fig 4, a hierarchy of interconnect resources can be seen. There are long lines that can be used to connect critical CLBs that are physically far from each other on the chip without inducing much delay. Theses long lines can also be used as buses within the chip.

There are also short lines that are used to connect individual CLBs that are located physically close to each other. Transistors are used to turn on or off connections between different lines. There are also several programmable switch matrices in the FPGA to connect these long and short lines together in specific, flexible combinations.

Three-state buffers are used to connect many CLBs to a long line, creating a bus. Special long lines, called global clock lines, are specially designed for low impedance and thus fast propagation times. These are connected to the clock buffers and to each clocked element in each CLB. This is how the clocks are distributed throughout the FPGA, ensuring minimal skew between clock signals arriving at different flip-flops within the chip.

In an ASIC, the majority of the delay comes from the logic in the design, because logic is connected with metal lines that exhibit little delay. In an FGPA, however, most of the delay in the chip comes from the interconnect, because the interconnect - like the logic - is fixed on the chip. In order to connect one CLB to another CLB in a different part of the chip often requires a connection through many transistors and switch matrices, each of which introduces extra delay.


4. FPGA programmable interconnect (courtesy of Xilinx).

Clock Circuitry: Special I/O blocks with special high drive clock buffers, known as clock drivers, are distributed around the chip. These buffers connect to clock input pads and drive the clock signals onto the global clock lines described above. These clock lines are designed for low skew times and fast propagation times. Note that synchronous design is a must with FPGAs, since absolute skew and delay cannot be guaranteed anywhere but on the global clock lines.

SRAM vs. Antifuse vs. Flash
There are three competing technologies for programming FPGAs. SRAM programming involves a small static RAM bit for each programming element. Writing the bit with a zero turns off a switch, while writing with a one turns on a switch. Another method involves an antifuse that consists of a microscopic structure that, unlike a regular fuse, normally makes no connection. A large amount of current during programming of the device causes the two sides of the antifuse to connect. A third and relatively new method uses flash EPROM bits for each programming element.

The advantages of SRAM-based FPGAs - the most common programming technology by far - is that they use a standard fabrication process that chip fabrication plants are always optimizing for better performance. Since the SRAMs are reprogrammable, the FPGAs can be reprogrammed any number of times, even while they are in the system, just like writing to a normal SRAM. SRAM devices can easily use the internal SRAMs as small memories in the design.

The disadvantages of SRAM-based FPGAs are that they are volatile, which means a power glitch could potentially corrupt the contents of the device. SRAM devices have large routing delays and are slower than other technologies, in theory, but continually improving SRAM technology has effectively eliminated this disadvantage. SRAM FPGAs can consume more power and are less secure than other technologies because they must be reprogrammed upon power-up and the programming bitstream can be observed going into the device. Custom SRAM FPGAs with built-in keys that unencrypt incoming program bit streams can be purchased from vendors, but this reduces the low cost and fast lead time advantage of the FPGA. Bit errors are also more likely with SRAM FPGAs than with the other devices. The market has decided that the advantages of SRAM FPGAs outweigh the disadvantages as they are by far the dominant FPGA technology.

The advantages of antifuse FPGAs are that they are non-volatile and the delays due to routing are very small, so they tend to be faster. Antifuse FPGAs tend to require lower power and they are better for keeping your design information out of the hands of competitors because they do not require an external device to program them upon power-up as SRAM devices do. The disadvantages are that they require a complex fabrication process, they require an external programmer to program them, and once they are programmed, they cannot be changed. The complex, nonstandard fabrication process has turned out to be a key disadvantage as antifuse FPGAs have lower yields and the technology has improved more slowly than SRAM FPGAs.

Flash FPGAs seem to combine the best of both of the other methods. They are nonvolatile like antifuse FPGAs, yet reprogrammable like SRAM FPGAs. They use a standard fabrication process like SRAM FPGAs and they are lower power and secure like antifuse FPGAs. They are also relatively fast. Currently, one vendor supports flash FPGAs and another vendor has a hybrid flash/SRAM FPGA. They are not catching on as fast as I expected, though that could change in the future.

Example FPGA families
Examples of SRAM FPGA families include the following:
  • Altera Stratix II and Cyclone II families
  • Atmel AT6000 and AT40K families
  • Lattice LatticeEC and LatticeECP families
  • Xilinx Spartan-3 and Virtex-4 families
Examples of antifuse FPGA families include the following:
  • Actel SX and Axcelerator families
  • Quicklogic Eclipse II family
Examples of flash FPGA families include the following:
  • Actel ProASIC family
Examples of hybrid flash/SRAM FPGA families include the following:
  • Lattice LatticeXP family
Emerging technologies
Cores: When I talk about a "core" I am simply referring to a large self-contained function. There are two basic types of cores. The soft core, known as an IP core, is a function that is described by its logic function rather than by any physical implementation. Soft cores usually consist of hardware description language (HDL) code. Hard cores, on the other hand, consist of physical implementations of a function. With respect to FPGAs, these hard cores are known as embedded cores because they are physically embedded onto the chip die and surrounded by programmable logic.

Many FPGA vendors have begun offering cores. The density of programmable devices is increasing, enabling what is called a Programmable System on a Chip (PSOC). Whereas programmable devices were initially developed to replace glue logic, entire systems can now be placed on a single programmable device. SOCs include of all kinds of complicated devices, like processors. In order to place these complex functions within a programmable device, there are three options: the first is to either (a) design the function yourself and place it in the programmable logic, (b) purchase the HDL code for the function and incorporate it into your HDL code, or (c) get the vendor to include the function as a cell embedded in the programmable device. The second option is the IP core or soft core, while the third option is the embedded core or hard core.

IP Cores: IP cores are often sold by third party vendors that specialize in creating these functions. Recently, FPGA vendors have begun offering their own soft cores. IP cores reduce the time and manpower requirements for the FPGA designer. IP cores have already been designed, characterized, and verified. Also, IP cores can often be modifiable, meaning that you can add or subtract functionality to suit your needs. They are also portable from one vendor to another.

But IP cores may also be expensive. Electrical characteristics such as timing or power consumption for IP cores can be optimized to a limited degree, but the actual characteristics depend on its use in a particular device and also depend on the logic to which it is connected. IP cores purchased from a third party may not be optimized for your particular FPGA vendor's technology. You may not be able to meet your speed or power requirements, especially after you have placed and routed it.

Embedded Cores: The embedded core is ideal for many users, which is one reason why programmable device vendors are now offering embedded cores in their devices. The embedded core will be optimized for the vendor's process to give you good timing and power consumption numbers. The function will be placed as a single cell on the silicon die and so the performance of the function will not depend on the rest of your design since it will not need to be placed and routed.

Some embedded cores are analog devices that cannot be designed into an ordinary FPGA. By integrating these functions into the device, you can avoid the difficult process of designing analog devices, and you save the chips and components that would otherwise be required outside the programmable device.

Of course there is a drawback to embedded cores. By using an embedded core in your programmable device, you tie your design into a single vendor. Unless another vendor offers the same embedded core, switching to another vendor will require a large effort and will not be pleasant.

Processor Cores: Processor cores are one of the types of cores commonly available as IP cores or embedded cores. These processors tend to be those that are designed for embedded systems since, almost by definition, programmable devices are embedded systems.

If the processor core is embedded, you will be using a processor that has been optimized and has predictable timing and power consumption. For either type of core, tools will be readily available for software development. Off-the-shelf cross compilers and simulators can be used to debug code before the design has been completed and the programmable device is available.

An example of an FPGA with an embedded processor, along with other embedded cores, is shown in Fig 5.


5. FPGA with embedded processor core (courtesy of Quicklogic).

DSP Cores: Digital Signal Processors (DSPs) are another common type of core that is offered as an IP core or an embedded core. These are essentially specialized processors that are used for manipulating analog signals. They are commonly used for filtering and compression of video or audio signals.

Many engineers have argued that as general processors become faster, DSPs will be less useful because the same functions can be accomplished using the generic processors. However, video and audio digitization, compression, and filtering requirements have increased in recent years as millions of users connect to the Internet and regularly upload and download all kinds of information over relatively limited bandwidth connections. So far, DSP demand for use in networking and graphics devices has been increasing, not decreasing.

Analog Cores: FPGA vendors have begun to include analog cores in their FPGAs. For example, PHY cores are the analog circuitry that drives networks. Many companies are now integrating this functionality onto their devices. Because these devices include specialized analog circuitry, they are available only as embedded cores.


6. FPGA with embedded PHY core (courtesy of Actel).

A functional block diagram of an FPGA that includes an embedded processor core, embedded digital peripheral cores, and embedded analog cores is shown in Fig 6.

Special I/O Drivers: Special I/O drivers are also being embedded into programmable devices. The newer buses inside personal computers need to have very tightly controlled timing and must be driven by special high-drive, impedance-matched circuits. The I/O buffers need to have inputs with very specific voltage threshold values. Many vendors now offer programmable devices with I/O that meet these special requirements. Many times, this is the only way to design a programmable device that can interface with these buses without external chips and components.

New Architectures: New basic architectures are being developed for the logic blocks that comprise FPGAs. One new architecture has a logic block that is based on a DSP, as shown in Fig 7. This type of FPGA will be better for use in chips that need a significant amount of signal processing. I have certain doubts about this future path, though. First, the majority of programmable devices do not perform any DSP, so this architecture targets a relatively small market. Second, special tools will be needed to convert digital signaling algorithms for use in such a specialized FPGA. These tools will need to optimize the algorithm very well so that performance in this specialized FPGA can actually perform better than a standard DSP, or a generic processor, running code that has been optimized using tools and compilers that have been available for years.


7. DSP core cell in an FPGA (courtesy of Altera).

New tools
The most significant area for the future, I believe, lies in the creation of new development tools for FPGAs. As programmable devices become larger, more complex, and include one or more processors, there is a huge need for tools to take advantage of these features and optimize the designs.

As FPGAs come to incorporate processors, development tools are needed for software just as much as for hardware. Hardware synthesis tools allow hardware engineers to work at higher levels of abstraction, without the need to understand the details of the underlying hardware architectures. Similarly software synthesis tools are needed to allow software engineers to work at a higher level of abstraction without the need to understand the details of the underlying software architecture.

Ultimately, there will have to be a melding of hardware and software expertise in an FPGA designer. System level issues must be understood and addressed. Future intelligent tools will work with libraries of pre-tested hardware objects and software functions, leaving "low-level" C and Verilog design necessary only for unique, specialized sections of hardware or software.

Eventually, platform FPGAs with embedded processors will become the dominant platform for embedded system design, and will finally allow the fulfillment of the promise of, and force further development of, hardware/software co-design tools.

Conclusion
This article has presented an overview of current and emerging FPGA technologies, architectures, and tools. You are now prepared to delve into your first or fiftieth FPGA design with the confidence that your knowledge is up to date and that you have the ability to accurately evaluate the various FPGA vendors and their families, and the software tools needed to ensure your design works as required.

Bob Zeidman is the president of Zeidman Technologies (http://www.zeidman.biz/), a company that develops hardware/software co-design tools. He is also president of Zeidman Consulting (http://www.ZeidmanConsulting.com/), a contract research and development firm. Among his publications are technical articles on hardware and software design methods as well as three textbooks: Designing with FPGAs and CPLDs, Verilog Designer's Library, and Introduction to Verilog. Bob holds two patents and earned bachelor's degrees in physics and electrical engineering at Cornell University and a master's degree in electrical engineering at Stanford University. Bob can be contacted at Bob@ZeidmanConsulting.com.

All material on this site Copyright © 2006 CMP Media LLC. All rights reserved

2006년 4월 25일 화요일

VHDL Syntax

VHDL Syntax (IEEE Std 1076-1987)
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http://mikro.e-technik.uni-ulm.de/vhdl/vhdl87_syntax.html

VHDL Syntax (IEEE Std 1076-1993)
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http://mikro.e-technik.uni-ulm.de/vhdl/vhdl93_syntax.html

VHDL samples (references included)

Source: http://www.csee.umbc.edu/help/VHDL/samples/samples.html

The sample VHDL code contained below is for tutorial purposes.An expert may be bothered by some of the wording of the examplesbecause this WEB page is intended for people just starting tolearn the VHDL language. There is no intention of teachinglogic design, synthesis or designing integrated circuits.It is hoped that people who become knowledgeable of VHDL willbe able to develop better models and more rapidly meet whatevertheir objectives might be using VHDL simulations.

Verilog Coding Styles for Synthesis

Source: http://ee.ucd.ie/~finbarr/verilog/

Synthesizeable Verilog Code Examples
This page gives FREE synthesizable verilog code examples, block diagrams and timing diagrams of typical digital circuit building blocks.
Last update August 2000

2006년 4월 7일 금요일

uCdot | Getting Started with uClinux

http://www.ucdot.org/article.pl?sid=02/09/03/1357255

This article shows how to get started with uClinux on the Pilot and ARMulator emulators. As no hardware is needed it's a good way to get your feet dirty in uClinux.

커널 2.6 Intro

커널 2.6 Intro  (2006/03/21)

커널 2.6에 대한 간략한 소개와 커널 컴파일에 대해 설명하고 있는 KLDP 위키 문서 입니다

링크만 걸어드릴게요 ^_^

http://wiki.kldp.org/wiki.php/Kernel%202.6%20Intro