ChipX | About Structured ASIC

About Structured ASIC

Structured ASICs are a category of custom devices that approach the performance of today's Standard Cell ASICs, while dramatically simplifying the design complexity and project risk. Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O. By virtue of the predefined structures, the ASIC vendor can design any time-consuming task – such as test, signal integrity and IR drop – into the architecture.

Structured ASICs simplify the complexity of custom silicon design by providing a fabric of identical building block cells that are prearranged in a series of sizes and complexities. The design task involves mapping the design into a "blank slate" of silicon by choosing from a large library of building block cells, and interconnecting them as necessary. Only the top layers need be customized, allowing the design to benefit from faster turnaround time and reduced complexity as well as more favorable NRE. By choosing 2, 3, or 4 customizable metal layers, the designer is in complete control of the trade-off between density, cycle time, and mask complexity.

Gate Arrays, the ancestor of Structured ASICs, consists simply of an array of gates in the pre-defined layers of metal. This leads to congestion when routing more complex designs and a great deal of unused silicon. Structured ASICs address this problem by using logic cells to achieve maximum local flexibility, density and higher performance. Also, Gate Arrays typically do not include hard IP such as memory, processors, analog cores and physical layer components. Structured ASICs lend themselves easily to IP inclusion, tuning the surrounding fabric to accommodate each specific hard IP element.

Standard Cell ASICs, which use a full set of masks for fabrication, is the approach of choice for very high volume, stable designs as well as highly complex designs exceeding 3 million gates. Once a design has been proven in the market and is facing predictable high volume price pressure, Standard cell ASICs deliver the best efficiency and economy. However, when time to market, flexibility and risk mitigation are critical, Standard Cell has a number of shortcomings. First and foremost, Standard Cell designs are extremely complex and therefore take an average of 2-3 years to develop. The fabrication time is long and costs are astronomical. Structured ASIC designs can be quickly and economically built and they can be modified just as quickly. Standard Cell ASIC designs also carry a burden of higher risk (at a higher cost) for design success. Every Standard Cell ASIC is a full custom design with untested elements at every layer. Structured ASICs reuse 90% of their tested design elements, giving higher confidence in design success and time to market.

FPGAs are electrically programmable logic devices that often have integrated IP such as processors, memory and other complex macro elements. The major advantage of FPGAs is flexibility. Changes can be made quickly and even remotely. However, this flexibility is possible at the expense of footprint area, power consumption and unit cost. FPGA designs trade power and density for flexibility and performance. Once a design has passed its low volume prototype phase, it must be converted to an ASIC in order to achieve performance, power and economic targets of the production marketplace.

Every design has a phase in its life cycle where an FPGA, a Standard Cell ASIC or a Structured ASIC is most viable. Ideally, an FPGA prototype will be converted into a Structured ASIC in production and once a design reaches predictable high volume, the Structured ASIC will be converted easily into a Standard Cell ASIC using the same supplier, tools and manufacturing process.

SideChip™ Architecture

A SideChip™ is a Structured ASIC that resides next to a main ASIC and provides integration relief and flexibility to a system architecture. In a growing number of systems where standards are changing, and markets are fragmented, designers need to expand the capabilities of the system but cannot afford to re-spin the main system chip or build a new chip for each individual market. By mounting additional capabilities on a ChipX SideChip™, designers can meet changing market requirements and extend the life of an existing system with minimal effort.

Learn More

• Structured ASIC Overview (UCLA)
• Assessing the Structured-ASIC Alternative (EE Times)
• Flexible "Partner" Chip can be an SoC's Best Friend (EE Times)
• The Promise of Structured ASIC (Electronics Weekly)

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