Verilog Coding Style for Efficient Digital Design

Kapil Batra (STMicroelectronics Ltd., India, Kapil.batra@st.com), Mohammad Suhaib Husain (msuhaib@hotmail.com)

Abstract: In this paper, we discuss efficient coding and design styles using verilog. This can be immensely helpful for any digital designer initiating designs. Here, we address different problems ranging from RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All these problems are accompanied by an example to have a better idea, and these can be taken care off if these coding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however, here we try to cover a few of them.

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