버퍼/스토리지
게재:2009년08월19일
예일 대학교(Yale University)와 SRC(Semiconductor Research Corp.)사의 연구진들은 강유전체가 플래시보다는 DRAM을 대체하는 데 적합하다고 주장하고 나섰다. 현재의 DRAM 기술은 수 밀리초마다 한 번씩 재생을 시켜줘야 한다. 하지만 강유전체 물질은 재생 없이 수 분을 지탱할 수 있기 때문이다.
최근 예일 대학교와 SRC사의 연구진들은 FeDRAM을 위한 실험용 강유전체 트랜지스터를 시연했다. 이는 DRAM보다 1,000배 정도 오랫 동안 정보를 기억하고 전력 소모가 20배 이상 적으며 ITRS(International Technology Roadmap for Semiconductor)의 최신 노드에도 맞게 스케일링 될 수 있다고 그들은 밝히고 있다.
그럼 이제부터 FeDRAM의 이점에 대해 보다 자세히 살펴 보자.
R. Colin Johnson
EE Times
PORTLAND, Ore. ─ For over a decade, materials researchers have sought a ferroelectric material that could work in flash-sized bit cells that retain information for as long as a decade--the base requirement for nonvolatile memories.
Researchers at Yale University and the Semiconductor Research Corp. (SRC) claim that ferroelectrics are more appropriate for replacing DRAM than flash. Current DRAM technology has to be refreshed every few milliseconds; ferroelectric materials could last minutes without freshing.
Yale and SRC researchers recently demonstrated an experimental ferroelectric transistor for FeDRAMs that retained information 1,000 times longer than DRAMs, consumed 20 times less power and can, they claim, be scaled to even the most advanced nodes on the International Technology Roadmap for Semiconductors.
"Our memories are as fast a DRAM, if not faster, but are as small as flash, and more scalable," claimed Yale engineering professor Tso-Ping Ma. "Flash runs into a brick wall at 25-nanometer node, but FeDRAMs can scale as small as CMOS, which could extend below the 10-nanometer node."
Ferroelectric memories use oxides like lead zirconate titanate that spontaneously form into nanoscale dipoles that can be electrically switched. To make memories nonvolatile, chip makers must shield bit cells from the depolarization fields normally created by the circuitry of silicon chips. The resulting package size makes them non-competitive with flash.
On the other hand, FeDRAMs combine the virtues of both DRAM and flash, and potentially could scale to smaller sizes since a bit cell is essentially a CMOS transistor using a ferroelectric material for its gate oxide.
"Several chip makers have nonvolatilie FRAMs, but they shield the bit cell from depolarization fields by sandwiching the ferroelectric material between two metals, making their cell sizes too large to be competitive with flash," said Ma. "But our cell sizes are very competitive [with] flash."
Ferroelectric materials also dovetail with current trends in advanced transistors, in particular with the use of high-k dielectrics. CMOS transistor sizes are limited by the thickness of their gate oxides, which are approaching the atomic scale. To scale below 32 nanometers, semiconductor makers have had to switch to high-k dielectrics to prevent gate oxides from getting too thin.
Ferroelectric materials are even higher-k materials than the dielectric used in today's transistors, offering a clear path to advanced processing nodes, according to Yale an SRC.
"Ferroelectric materials have a 'k' [relative dielectric constant] of least 100 compared to about 20 for other high-k dielectrics, enabling our design to scale five times further," Ma claimed. "The downside is that semiconductor makers have traditionally been afraid of ferroelectric materials. However, now that they have gained some experience with using high-k dielectrics, there won't be as much resistance." Yale's FeDRAM bit cells also are simpler than traditional DRAM bit cells, which require an extra component (a capacitor) to store a charge. FeRAM bit cells consist of a single CMOS transistor with its gate oxide replaced with a high-k ferroelectric material for storage.
"Their No. 1 advantage is the retention time of a FeDRAM, which is improved about 1000 times over conventional DRAMs, which means that refreshing can be done much less frequently," said Kwok Ng, SRC's director of device sciences. "The second advantage is scaling: In a normal DRAM the capacitor has to be big enough to hold the charge, and consequently takes up most of the area, which makes it very hard to scale. But there is no capacitor in a FeDRAM bit cell, so it is much easier to scale down to smaller sizes."
The third advantage, according to Ng, is power consumption during read/write operations. The researchers report a 20-fold decrease since no DC current was required to transfer the charge to the capacitor. DRAMs must pump a charge onto the storage capacitor. FeDRAMs can use a simple AC voltage potential to polarize the gate dielectric.
Rather than accumulating charge, FeDRAMs work by memorizing a shift in threshold voltage, which is the same principle used by flash memory to store multiple bits per cell. This is one of the directions Yale and SRC researcerhs plan to explore next.
The researchers also designed arrays, and will demonstrate working FeRAM arrays next year. So far, preliminary tests indicate that as many as 1 trillion read/write cycles are possible for FeDRAMs, but characterization of long-term reliability msut still be documented.
< Originally from 08/12/2009 >
==========
출처: http://www.eetkorea.com/ART_8800581640_839576_NT_950d34f8.HTM
댓글 없음:
댓글 쓰기