May 21, 2008
How to design portable handsets using CPLDs
This tutorial describes the different ways in which CPLDs can be used to address the shortcomings associated with handset platforms.
By Michael Gordon, Xilinx
Portable consumer electronic designs such as cell phone handsets, PDAs, and MP3 players are typically very high-volume products. Because of this, product designers first look to ASIC or ASSP methodologies to pack the greatest functionality into tiny, portable packages. But CPLDs are rapidly becoming a more attractive proposition in this market as they meet the density and power requirements of many portable applications while adding the ever more important benefit of helping customers quickly create designs that seize market opportunities. They also help designers overcome many of the shortcomings of popular handheld platforms such as OMAP-, XScale- or i.MX.
The emerging need for flexibility
Using an ASIC or ASSP will typically meet a design project's specifications for functionality and power consumption. However, there are other factors design groups targeting the consumer market must take into account. And a chief emerging factor is flexibility. Indeed the consumer world is rapidly changing and features your team envisioned at one point in time can become obsolete within a matter of months, as you and your competitors react to ever-changing technologies and market dynamics to deliver differentiated solutions.
As the consumer electronics business becomes much more competitive, design teams need to make design choices that will allow them to produce the right products at the right time to ultimately help their companies sustain and hopefully build market share. But this need to be agile in the market and makes picking the correct ASSP or designing the right ASIC a very difficult task.
Today's designers are now looking beyond the fixed architecture of ASICs and ASSPs to discover the innate design flexibility and time-to-market benefits of programmable logic. Today's low power CPLDs offer portable device designers a viable alternative to standard cell technology and provide some of the lowest cost, lowest power solutions.
Various CPLD families are now priced low enough that they are comparable in price to discrete logic devices but give design groups the added benefit of modifying their designs quickly to seize market opportunities.
Let's examine ways to expand beyond the limitations of today's ASIC/ASSP portable handset solutions, with simple, cost-effective, low-power programmable logic using CPLDs. As most handsets today are OMAP-, XScale- or i.MX-based designs, we'll describe how CPLDs can offer solutions to several problems that commonly pop up with these portable mobile platforms.
Level translation
A very common problem designers encounter today is interfacing two chips that have different voltage requirements. Memory vendors typically do not make memories at every voltage level, yet MPU vendors typically offer devices at several voltage levels. Design groups can overcome this problem by using level translators, but level transistors are expensive and often more area in the system, which can add cost to the design. Using a CPLD is a better solution and offers substantially greater flexibility. Many CPLDs are capable of translating between two voltages, and some can handle as many as four.
Some CPLDs' I/O banks easily translate between voltages ranging from 1.5V to 3.6V in a single chip, as shown in Fig 1. But CPLDs also have the added benefits of programmability. You get that same translation as part of the whole package, which means you get a bundle of logic, flip-flops, power reduction resources, and I/O buffers frequently priced below level translator chips.
1. CPLD-level translation of TI OMAP signals.
Pin expansion
In general, high pin-count ASICs are more expensive than low pin-count ASICs. If your design project's logic needs dictate a low capacity, but your I/O requirements dictate a high capacity, you may be paying for logic you will never use to gain the pins. One solution to this is adding a CPLD to operate as a "pin expander," as shown in Fig 2.
2. CoolRunner-II CPLD pin expansion of XScale processor.
The basic idea is to identify GPIO pins that typically operate at a slow speed. Then, rather than assign ASIC pins to them, attach the CPLD pins to the slow-moving GPIO signals, serialize the signals, and import them to the ASIC on fewer net pins. You can perform serializing/deserializing through simple, efficient shifting, and can drop the pin counts dramatically on expensive ASICs.
As an alternate viewpoint, OMAP, XScale and i.MX processors provide specific pin mixes to support the applications their vendors deem appropriate. But you don't have to strictly follow their advice, which some deem as limitations. CPLD pin expansion permits you to create your own GPIO pins of assorted voltages and additional capabilities (such as pulsing, PWM, or individually 3-stated).
Pin swizzling
CPLDs also allow you to rearrange your pinouts when your team discovers PCB layout errors. This valuable quality is key to keeping you on schedule and within financial and power budgets. Correcting misconnections on a board without having to re-spin the PCB can shave weeks and even months out of product schedules.
Many CPLD logic arrays can reassign pin logic at will. You will be amazed at how well these devices retain pinouts through multiple edits, yet permit you to re-assign a design onto different pins as needed. Various CPLD companies offer data sheets that explain the architecture and point you to application notes that give all the detail you will need to understand the value of CPLDs.
Power control
Quick power up is one of the big strengths of CPLDs. The devices typically contain their own configuration cells. Designers can configure these cells, so when users activate a handset, the CPLDs power up first and direct the activities of other chips. CPLDs for example can control and sequence some power regulators as well as other controlling signals that design groups typically need to define early and correctly in board operation. Programmable logic vendors have application notes that describe some of these capabilities.
Power reduction
XScale-, OMAP- and i.MX-based chipsets all include some version of the ARM microprocessor. This is not a surprise as ARM pioneered and has focused on developing low power processors. But over the years, many design groups, including ARM licensees, have added their own methods to further reduce processor and overall system power consumption. Today, it isn't uncommon for design groups to use several power reduction operations such as clock gating, voltage throttling, and on-board memory management to reduce transfers within the device. These are sometimes referred to as run, wait, doze, sleep, and hibernate.
In addition to hardware techniques that reduce power, operating systems like Symbian have "power awareness" features that allow systems designers to ration power and assign power to processor functions on an as needed basis, keeping unused resources powered in the lowest possible power mode when they are not in active use. This all works well and lowers processor power. However, lowering power in the rest of the system exceeds the scope of these methods. Enter CPLDs again. Vendors design many of their CPLDs to be low power. You can use clock dividers and other power-saving technologies available in many CPLDs to reduce power in many (if not all) of the chips on your design. You can configure the devices to block power to other chips, which also reduces the amount of electromagnetic fields propagating on your board and emanating from your system.
Logic Consolidation Having three two-input AND gates, two three-input OR gates, and a Schmitt buffer package on your board can burden your bill of materials (BOM), eat away at your power and cost budgets, and lower your reliability. Collecting that stray logic into a consolidated, low power CPLD not only solves these problems, but stores additional unused logic right there, on your board – ready to use with future improvements/edits.
Conclusion
In conclusion, CPLDs are quickly becoming a top choice for design groups trying to seize opportunities in the portable consumer space. CPLDs offer low-power, low-cost, high-volume, and what's more great flexibility for portable consumer products.
Engineers designing portable products can use CPLDs devices in many ways and to solve many problems. The devices can make life much easier for designers building systems with OMAP, XScale and i.MX processors, but CPLDs work just as well with many other processors to add functionality, save power, and get products to market fast.
While it may be some time before we see a big FPGA on a cell phone, it shouldn't surprise anyone to see in the not too distant feature CPLDs in the heart of the latest and greatest portable devices.
Prior to joining Xilinx in 2000, Michael worked at various semiconductor and disk drive companies, holding a variety of finance and product management positions.
Michael holds a master's degree in finance and international business from Santa Clara University and a bachelor's degree in finance from San Jose State University.
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