Programmable Logic DesignLine
(05/20/2009 4:18 PM EDT)
Editor's note: People are saying more frequently that power has become the No. 1 issue for those designing with programmable logic. Not coincidentally, it has also frequently been the central topic of design how-tos and other resources posted at Programmable Logic DesignLine.
To that end, we've gone back through the material posted over the past year or so and pulled out what we think are some of the best resources for power-conscious designers comparing, selecting and working with FPGAs and other programmable logic devices.
How to reduce power consumption in CPLD designs with power supply cycling
By Gordon Hands, Lattice Semiconductor
This three-part article covers several aspects of FPGA power consumption; it also provides a new look at power dissipation numbers, and questions the traditional methods of estimating and measuring power.
Power-aware FPGA design
By By Hichem Belhadj, Vishal Aggrawal, Ajay Pradhan, and Amal Zerrouki, Actel
This three-part article covers several aspects of FPGA power consumption; it also provides a new look at power dissipation numbers, and questions the traditional methods of estimating and measuring power.
Part I
Part II
Part III
Innovative heat sink designs cool "hot" FPGAs
By Barry Dagan, CTO, Cool Innovations
This article is intended to help engineers looking for more-powerful heat sinks by describing recent innovations in heat sink design and analyzing their impact on heat sink performance.
How to perform meaningful benchmarks on FPGAs from different vendors
By Seyi Verma, Altera
A suite of unbiased and meaningful benchmarks that truly compare the hardware architectures and software design tool chains from the major FPGA vendors.
Tips on using CPLDs to reduce system processor power consumption
By Mark Ng, Xilinx
This paper details how to use a low-power CPLD to offload operations of the microprocessor so it can stay in its low-power state longer.
Top 10 tips to minimize power consumption when designing with FPGAs
By Christian Plante, Actel
With stricter system power limits, specifications and standards that put a cap on the total power consumed, system designers are increasingly challenged. This paper presents the key Dos and Don'ts to help designers manage power budgets with FPGAs.
Webinar: Creating Power-Optimized Designs with Virtex-6 and Spartan-6 FPGAs
Xilinx
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