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출력시간: 2008-09-03 13:43:38
PLDWorld 홈페이지의 유지보수를 위해, 여기저기 서핑중 발견되는 각종 자잘한 & 미쳐 정리가 되지않은 나만의 자료와 더불어 나의 "일상다반사"가 하나하나씩 저장되는 곳... 나중에 정리되는 Contents들은 그때마다 하나씩 없어질런지도... :)
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출력시간: 2008-09-03 13:43:38
| Copyright ⓒ DigitalTimes All Rights Reserved. |
포스팅 할 곳은 이대후문에 있는 <제시카 키친>.
친구들과 선유도로 나들이 갔다가 저녁을 먹기 위해 간 곳이다.
친구 중에 한 녀석이 미리예약을 해서 갈 수 있었던 곳.
이곳은 손님이 많아서 예약을 하지 않으면 먹기 힘들다고 한다.
<제시카 키친>에 대해 말하기 전에 먼저 다녀온 <선유도>에 대해 잠시 얘기하련다.
아직 선유도를 못 가본 사람이 있다면 참고, 또 참고 하길!
선유도는 정말 사진 찍기에 좋은 곳인 것 같았다.
동호회에서 단체로 출사 나온 듯한 사람들도 많이 보이고 말이지..
가족단위로 나들이 나온 분들도 많았고..
하지만 선유도.. 그곳은 커플들의 천국이었다.
솔직히 커플이 무슨 죄겠는가, 하지만 눈에는 거슬렸다. -_-+
솔로들은 이점 염두에 두고 선유도로 나들이 나가길.
혹여 지나가던 연인들이 혀짧은 소리내며
행복에 겨워하는 모습을 보이더라도 그냥 그러려니 하길.
나와 친구들은 주린 배를 움켜잡고, 선유도 곳곳의 커플들을 뒤로 하고 밥을 먹으러 갔다.
우리의 허전함을 맛난 음식으로 달래주었던 <제시카 키친>.
<제시카 키친>의 입구.
우리가 입구로 들어갔을 때, 아무도 없어서 잠시 당황.
곧 담당자가 와서 예약한 자리로 안내해 주었다.
<제시카 키친>은 샐러드 바다.
안으로 들어가기 전에 밖에 있는 알림판을 찍어봤다.
솔직히 싼 가격은 아니다. 거기다 부가세까지 별도~ -0-
<제시카 키친>은 첨 가보는 거였지만, 친구가 적극 추천하기도 했고,
분위기도 나름 맘에 들어서 안으로 입장~
(니가 안들어가면 어쩔껴~ ㅋㅋ)
실내는 상당히 널찍했다.
각 요리별로 바가 있어서 원하는 음식을 가져다 먹는다.
즉석요리(왕새우 구이, 립, 스테이크 등)는 바 앞에 가서 달라고 하면 바로 만들어 준다.
우리가 갔을 때가 오후 5시쯤이었는데, 안쪽 창가 자리는 이미 다 차있다.
오늘의 스프는 보리스프와 양송이스프~
사실 난 스프를 별로 좋아하지 않는다.
스프는 배만 부른 것 같은 느낌.. -_-
그래서 먹지 않음. 먹은 친구의 평을 전하자면 맛있단다.
스프를 상당히 좋아하는 친구인데, 웬만하면 맛있다는 얘기를 잘 안한다.
그런데 맛있다고 한 걸 보면 맛있긴 한가보다.
(물론 사람마다 입맛은 다르겠지만.. ^^)
샐러드와 과일이 놓여 있는 곳을 찍어 봄.
개인적으로 봤을 땐 세븐스프링스나 빕스보다 훨~씬 괜찮았다.
샐러드들은 신선하고, 종류도 많았다. 과일 역시.
아쉬운게 하나 있었다면 스테이크가 좀 질겼다는거~ -0-;
샐러드는 가져다 놓기가 무섭게 사라졌다.
즉석요리는 말할 것도 없고!
하지만 바로바로 음식을 채워주고, 만들어줘서
다른 샐러드바 처럼 오래 기다리진 않았다.
다른 음식들 먹는다고, 빵은 한 입 밖에 못 먹어 봤지만
부드러운게 맛있었다.
테이블에는 이렇게 올리브와 식초를 놓아두는데, 빵 먹을 때,
설명에서 처럼 올리브와 식초를 섞어서
여기다 찍어먹으면 더 맛있다.
빵 마다 질감과 맛이 달라 찍어먹을 때와 안 찍어 먹을 때의 맛이 다르다.
하지만 난 다 찍어 먹었다~ 캬하핫~ ^o^/
케익 바에는 여러 종류의 케익이 있었는데, 티라미슈가 제일 맛있었다.
그런데 찍은 줄 알았던 티라미슈 사진은 없군화.. ㅜㅜ
여러 종류의 카나페가 있었는데, 사진으로 담은 건 요거 하나.
이건 세 번째 접시!!
두 번째 접시까지 정신없이 먹다가 세 번째 접시에서 촬영..
역시 먹는게 먼저다~ 암! *_*
난 스테이크 보다 저기 아래에 있는 <목살 구이? 스테이크?>가 더 맛있었다.
위에서도 얘기했지만, 스테이크는 넘 질겼다.
스테이크를 먹을 바엔 립을 먹거나, 옥돔구이나 새우구이를 먹길 권한다.
<제시카 키친>의 전체적인 분위기는 이렇다.
조명도 좋고, 인테리어도 예뻤다. 창가 자리는 트인 느낌이 들어서 좋고.
그리고 내가 이곳에서 칭찬해 주고 싶은 점은 서버들의 친절한 서비스다.
신속하게 손님의 요구를 들어주고, 체크해준다.
커피 한 잔 마실까 해서 찾은 커피바~
커피바 옆에는 쿠키가 놓여 있지만,
과자를 좋아하지 않아 쿠키는 먹지 않았다.
하지만 먹음직 스럽게 놓여 있어서 사진으로나마 담아봤다.
내 이목을 끌었던 것은! 바로 이것! *_*
생맥주가 무료!
커피는 잠~시 접어두고 서버 언니께 맥주 한 잔 부탁~
차가운 잔에 담기는 것만 봐도 시원해지는 것 같다. ^^
맥주는 큰 기대를 하지 않고, 무료라길래 시켰던 건데, 맛은 기대 이상이었다.
맥주를 가져가면서 함께 가져간 아이스크림.
뉘집 아이스크림인지는 모르겠으나, 맛은 괜찮았다.
특히 모카맛 아이스크림 추천!
이것은 우리의 테이블.. 거의 막판의 모습이다.
5~6번 정도 정리가 된 후에 다시 이렇게..
뭔 음료를 저리 많이 먹었댜~ -0-
종류별로 가져다 먹음. ㅋㅋ
<제시카 키친> 매장은 센트럴시티점과 이대하늬솔점, 2군데 뿐이라고 한다.
센트럴점은 아직 못가봤지만, 다녀온 친구 말에 의하면
이대점이 분위기가 더 편안하고 좋다고 하니 참고.
<제시카 키친>은 가격이 조금 쎄긴 하지만, 그래도 다녀오면 후회는 안 할 곳이다.
무조건 싼 집만 찾는 사람들에게는 그다지 매력적이지 않은 곳일지도 모른다.
하지만 괜찮은 샐러드 바를 찾는 사람들에게는 적극 추천해주고 싶은 곳.
하늬솔 빌딩 방향으로 30m쯤 걸어가면
버스정류장 바로 뒤에
<제시카 키친>을 찾을 수 있다.
제시카 키친: http://www.jessicakitchen.co.kr
이대하늬솔점 전화번호: 02-362-1177
Actel steps up to battle PLD giants
Posted:26 Aug 2008
In the cut-throat programmable logic device (PLD) business, market leaders Altera Corp. and Xilinx Inc. tend to dominate the headlines.
The two FPGA giants tend to drown out their smaller rivals. But now, seeking to elbow its way into the spotlight and re-energize its bottom line, Actel Corp. recently acquired Pigeon Point Systems Inc.—a move that propels the FPGA house into the telecommunications computing architecture (TCA) components sector.
The world's fourth largest PLD/FPGA vendor also outlined its process roadmap. In fact, seeking to play catch-up in process technology, it is quietly skipping the 90nm node and devising a new line of 65nm PLDs and FPGAs.
Actel is also looking to turn up the volume in the noisy public relations wars in FPGAs, a slight departure from its relatively quiet nature. In other words, Actel hopes to avoid becoming a minor niche player destined for obscurity.
"In the area of static power FPGAs, we're killing the competition," said John East, president and CEO of Actel. "Actel is the leader in low-power FPGAs, but the problem is that nobody knows it."
Although Actel has some advantages, the company also has some "smart competitors," East told EE Times. "I like them. And they like me. But they want to kick my butt. Instead of kicking my butt, I want to kick their butts."
Road less travelled
Formed in 1985, Actel has taken a somewhat different road than its rivals. Initially, the company made its name by developing and selling FPGAs based on antifuse switching elements.
Later, it bucked the trend and developed products based on flash technology. In contrast, its main rivals sell FPGAs based on SRAM technology.
"Actel is well positioned for revenue growth with its current product offering," said Bryan Lewis, an analyst with Gartner Inc. "Actel has been attacking the low-power/low-cost portion of the FPGA market and this is where we are expecting most of the growth over the next three to five years. Actel gained market share in 2007 and we expect them to gain market share in 2008."
The PLD business includes several different product sectors, such as simple PLDs (SPLD), complex PLDs (CPLDs) and FPGAs. In total, the PLD/FPGA sector is expected to reach $3.8 billion in 2008, up 7.7 percent over 2007, according to Gartner.
In the PLD/FPGA sector, Xilinx was the leader in terms of market share in 2007, followed in order by Altera, Lattice and Actel. Last year, Actel was the only major vendor that grew in the arena. It had sales of $196 million in the PLD/FPGA sector, up 2.6 percent over 2006, according to Gartner.
Going forward, Actel hopes that trend will continue, as it seeks to remain a survivor in the competitive PLD business. At one time, there were 43 PLD vendors in the market, many of which are no longer around. Today, there are four main PLD players: Actel, Altera, Lattice and Xilinx. Another vendor, QuickLogic, has recently exited the mainstream FPGA market to focus on its ASSP products.
Now, there are several startups looking to turn the market upside down. Achronix, SiliconBlue and others claim to provide new and different approaches in the market.
But the PLD shakeout may not be over. One startup, MathStar Inc., recently moved to wind down its operations. As it seeks a buyer, MathStar said it plans to discontinue its field programmable object array (FPOA) chip development and its board-level systems development businesses.
Meanwhile, Altera and Xilinx appear to be in decent financial shape, but the two rivals continue to slug it out in a plethora of markets. Just which vendor will emerge stronger amid the current slowdown is unclear. Another PLD vendor, Lattice Semiconductor Inc., continues to spill red ink and its fate is unclear.
Moving forward
Actel appears to have bounced back, following a loss in 2007 and an ugly stock-option fiasco in 2006. But going forward, even Actel must find new markets— or niches—to remain relevant.
As for the new FPGA startups, these vendors face an uphill battle. Besides dealing with soaring design costs, the startups must find new customers who are willing to take a chance on a new architecture. "The probability for success (among the startups) is zero," East said. "It's too late for them."
Others wonder about the fate of FPGAs. PLDs compete for sockets against ASICs, and, to some degree, ASSPs. In general, FPGAs are limited in terms of their overall architecture, while ASSPs have some limitations in their customization, said Ronnie Vasishta, CEO of eASIC Corp., a supplier of structured ASICs, in a recent interview.
Not surprisingly, East disagreed that the party is over for FPGAs. ASICs, he argued, are falling by the wayside and remain too expensive. The ASIC market "is a sad place to be these days," he added.
ASICs are the least of Actel's worries. Perhaps the real challenge for the company is to find new markets, which are not dominated by industry heavyweights Altera and Xilinx. "FPGAs are a large business, but it's a dogfight," he said.
In simple terms, Actel is focusing on two sectors: low-power and systems management. Ranging in density from 3,000 to 4 million gates, Actel's FPGAs are aimed for automotive, commercial, industrial, and military applications.
Celestial success
One of its claims to fame is the satellite business. Over the last decade, Actel claims its FPGAs have been used in over 300 satellites and spacecraft, including GPS-2RM, Mars Reconnaissance Orbiter, Mars Explorer Rovers 1 and 2 (Spirit and Opportunity), Echostar, and Globalstar.
Citing the aerospace and other segments, Actel recently said revenues were $57.6 million for Q2 08, a 5 percent increase from Q1 08 and an 18 percent increase from Q2 07.
Actel has a net income of $1.964 million in the quarter, compared to $176,000 in the previous period and a loss of $2.645 million a year ago. For Q3, sales are expected to grow 1-3 percent sequentially. Wall Street is expecting a profit of $0.03 a share on sales of $57.05 million.
In Q1 08, Actel had record bookings. The company experienced shortages in the second quarter, but product demand "tailed off as the summer approached" and order rates were "subdued" heading into the third period, East said in a recent conference call with analysts.
East said visibility remains weak going forward, but he predicts a relatively "flattish" year in the overall semiconductor industry. What worries the semiconductor veteran is the current economic climate and oil prices, which, he said, could go as high as $1,000 a barrel in the distant future.
On the product front, fabless Actel is expected to make more introductions at or around the 130nm node. Its products are made on a foundry basis by Chartered, Infineon, Matsushita, UMC and Winbond.
Earlier this year, it rolled out two new members to its Igloo and ProASIC3 FPGA families starting at a record price of just 99 cents. The new 15,000-gate devices offer power consumption as low as 5 microwatts, 10 times less static power than more expensive CPLDs. Igloo is Actel's low-power FPGA solutions. The ProASIC line are low-power, flash-based FPGAs, which are nonvolatile and reprogrammable.
This month, it rolled out new ProASIC FPGAs to its military-qualified product offerings. Ranging in density from 600,000 to 3-million gates, the new low-power devices are immune to neutron-induced configuration upsets, according to Actel.
Sprint to 65nm
In process technology, however, Actel is behind by a wide margin. For example, Altera has recently taken the lead position in the process race, by recently rolling out a 40nm FPGA line. Rival Xilinx is competing with 65nm FPGAs.
To play catch-up in the process race, Actel has decided to skip the 90nm node and move to 65nm technology. Initial 65nm product tape outs are due early next year, according to East.
East insists the name of the FPGA game is low power—and not leading-edge processes. In fact, he claims that Actel's 130nm devices consume less power than Altera's 65nm products. "The days of smaller linewidths are over," he said. "Shrinks are not friendly in terms of power."
There are tradeoffs between flash- and SRAM-based FPGAs. The SRAM-based FPGA parts are generally suited for traditional and leading-edge consumer, military and wireless applications.
But SRAM-based products "have inherently high static power consumption," according to Actel. "Even 'low-power' SRAM-based FPGAs draw on the order of ten times more power than specified for typical battery-operated applications. SRAM-based FPGAs also experience power surges at start-up that drain batteries and can cause system-initialization failures. Compounding the problem, each process node 'shrink' increases the static power consumption of transistor-heavy SRAM-based FPGAs."
Besides its ongoing push in low power, Actel is moving into the systems management front by acquiring Pigeon Point Systems, a supplier of TCA components. Many OEMS devise their own TCA devices and boards. Pigeon Point's TCA products, which include controllers and reference design boards, are geared to replace proprietary architectures, especially in the telecommunications market.
Earlier this year, Actel and Pigeon Point announced a partnership to develop and market solutions based on the Actel's Fusion mixed-signal FPGAs, which would speed up the design of AdvancedTCA blade and AdvancedMC carrier blade management controllers. Fusion incorporates analog functions, embedded flash, and an FPGA fabric in a single chip, making it ideal for system management and intelligent power management.
"Pigeon Point is the de facto standard in the TCA arena," East said at the time of the acquisition. "As TCA experiences rapid deployment across the increasingly power-sensitive telecommunications, military and industrial markets, the merger of their market and technology leadership with Actel's power and system management solutions gives us [an] opportunity to capture a significant portion of the TCA system market."
Others had a slightly different viewpoint. "For either ATCA or MicroTCA, there is a real role for FPGAs in the shelf-control and power-control functions in the advanced mezzanine card," said Loring Wirbel, director of the EE Times' Market Intelligence Unit. " In fact, Altera has a big ATCA program. They think there will be more FPGAs used in those architectures than ASSPs. So Actel's probably just trying to bring some of that ATCA/MicroTCA expertise in-house. If they get into board-level evaluation systems, however, it could be a distraction."
- Mark LaPedus
EE Times
This article was printed from EE Times-Asia located at::
http://www.eetasia.com/ART_8800540940_480200_NT_5b4ebc4e.HTM
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출력시간: 2008-08-21 19:18:40
| Copyright ⓒ DigitalTimes All Rights Reserved. |
- Practical Chip Design - Blog on EDN - 1690000169
Tuesday, August 5, 2008
There is a long-standing debate in the industry over the future of FPGAs. The FPGA vendors have argued for years that their destiny is to replace ASICs as the way most digital systems are implemented. And in fact ASIC design starts have been falling for several years, as FPGA design starts have continued to rise, although these two numbers actually mean quite different things, making even a relative comparison murky.
But skeptics have pointed out that FPGAs themselves are vulnerable to replacement. ASIC vendors argue that they have not been losing design starts to FPGAs—they have simply been moving up-market, into the large SoC and mixed-signal designs of which FPGAs are incapable, hampered as the FPGAs are by limited density and performance, relatively high power consumption, and lack—with the exception of one Actel family—of configurable analog blocks. The decline in ASIC design starts has been not so much from incursion of FPGAs, the skeptics say, as from the simple fact that as integration goes up, the number of design starts necessary to complete a system goes down. Not many products require more than one SoC to be designed any more, especially in the dominant consumer electronics industry.
The most frequent conclusion from all of this debate has been that FPGAs own the logic prototyping world, having all but completely displaced big-iron logic verification systems. They also own the low-gate-count, low- to moderate-volume digital IC world: the space once occupied by gate arrays, and briefly the focus of the Structured ASIC movement.
But In recent months, we are seeing more tangible signs that this well-defined homeland for FPGAs may be under threat. First, we have seen attempts at incursion on the turf of Altera and Xilinx by what was supposed to be unthinkable: an FPGA start-up, SiliconBlue. The SiliconBlue product is still very much a conventional, SRAM-programmed FPGA, but the fact that a start-up could be funded and launched against such a mature industry infrastructure in itself implies cracks in the foundations.
The next indication came from what was supposed to be a moribund effort: the Structured ASIC world. This week Structured ASIC pioneer eASIC announced that not only did it have 120 design wins for its 90 nm product line, but that it was already working on customer designs for a 45 nm product family. The company's strategy not only cuts a swath across the sweet spot of the FPGA business—high-value, low- to moderate-volume SoCs—but it cuts into the conventional cell-based ASIC space as well. [Disclaimer here: the author has a small financial interest in eASIC, so be properly skeptical.]
It is not surprising that the Structured ASIC world is fighting back. The value proposition of the concept—an ASIC built on a pre-manufactured logic and memory array that could be configured using a few metal or via masks—was supposed to get better with each advancing process node, as cell-based design became harder and FPGAs fell further and further behind in power dissipation and system performance. In fact, based on eASIC's published numbers, that appears to be happening. Don't be at all surprised to see other vendors unveil structured products at 40 or 32 nm in the next couple of years. One interesting speculation: this could be a very interesting business proposition for a company with both foundry and IP assets and strong relationships in the fabless semiconductor industry, where many of the potential customers for such products are--someone like, say, a TSMC.
But wait, there's more. In a recent press event, Pierre-Yves Lesaicherre, senior vice president and general manager at NXP Semiconductor, made some very interesting remarks about the microcontroller market. Yes, microcontrollers—you know, the little 35-cent parts in ancient technology that run toasters? Think again.
Goeff Lees, vice president and general manager of the microcontroller product line at NXP, pointed out that far from being sponges for legacy fab capacity, 32-bit MCUs are closing in on the leading edge of process technology. "It's been a while since we designed a 32-bit microcontroller to run in a mature process, and that's a big change in strategy. A few years ago the MCU market was three years behind Intel's best production process technology. Now we are nine months behind," Lees said.
So what? Well, 32-bit microcontrollers, especially multi-core designs with sophisticated peripherals, are in many ways highly flexible ASSPs. That is really a more accurate characterization than to call them MCUs in anything but a purely architectural sense. As such, they can complete against ASSPs from fabless semiconductor vendors. But they can also compete against FPGAs, offering lower design time, higher performance, much better power consumption, and much lower price for large designs. In many ways, an application-targeted MCU is a reference design in silicon—almost literally to the point where all you do is modify a few software modules to differentiate your product.
And that is exactly what is happening, according to Lesaicherre. "Our microcontrollers have been eating into the bottom of the CPLD and FPGA markets," he said. As the computing power and memory on the dice improves—as it inevitably will, with 65 nm and 45 nm parts in design today—that appetite will extend to the heart of the FPGA market as well. The microcontrollers will be able to target a range of similar applications with a 32-bit processor cluster, a well-chosen accelerator or two, and a good set of peripherals. The compute-intensive, mostly standards-based tasks will go to the accelerators, and the differentiating features will go into software on the ARM cores.
It is a threat to both the FPGA and ASIC worlds—not just because it threatens to divert some design starts, but because—like the Structured ASIC threat—it attacks the heart of the FPGA business model. The big FPGA guys don't make their real money selling prototyping chips for $2,500 a piece. They make their money landing a design win for a medium-sized FPGA in early production, and then sticking in there as the product goes to moderate volumes—or in the case of Altera, shifting the volume to HardCopy as demand builds. And it is those moderately-complex, processor-based, few-million-gate SoCs in moderate volumes that will be most under threat from the alternatives. That is especially true for the MCU threat, since modern MCUs bristle with high-quality data-converters, giving them the analog functionality that FPGAs and Structured ASICs conspicuously lack.
This is not to say that any FPGA vendor is doomed. Nothing with momentum dies over night, and FPGAs still offer a strong value proposition in many areas—especially if the application allows the sort of cut'n'try design style for which the reprogrammable parts are beloved. None the less, it's going to be an interesting couple of years for the FPGA business.
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EDN Executive Editor Ron Wilson explores how IC design teams really work: the struggle for power efficiency and performance, wrestling with semiconductor processes and design methodologies, the challenges of global design teams. How do we somehow herd architecture, IP, design and verification into a successful tape-out?
- 출처: http://www.edn.com/blog/1690000169/post/190031219.html?nid=2435&rid=228590015
- 출처: http://www.edn.com/article/CA6565881.html?industryid=47039
SiliconBlue, a quiet startup with heavy FPGA-industry credentials, will go against the odds today by announcing its first product: a moderate-sized, moderate-performance FPGA family intended to be low enough in power and cost to be used in cellular handsets and other mobile devices. It's an audacious business move and an audacious claim, with some interesting technology behind it.
The company is claiming no huge breakthroughs in FPGA architecture or in process technology. In fact, according to founder and CEO Kapil Shankar, the SRAM-based logic fabric will look quite familiar to users of Spartan or Cyclone mid-sized FPGAs from the big guys.
"We didn't invent a new architecture here," adds the company's vice president of strategic marketing, industry insider John Birkner. "Our logic cell uses a four-input lookup table and a register, with a bypass path. It's actually based on the now-expired Xilinx patent from 1986." And SiliconBlue is fabricating its devices in TSMC's 65LP logic process, without significant modifications.
But the company is claiming significant reduction in power, saying that a 3500-logic-cell device can operate at 32 MHz while drawing only 9 mA from its 1.2V supply. The entire question of FPGA power consumption is hugely complex due to the lack of benchmarks, the wide array of activity profiles, various kinds of standby and sleep modes, and architectural approaches to reducing clock frequency that become factors in comparing power. But it does appear at first look that the SiliconBlue parts are showing significantly lower operating power on similar tasks than their mainstream competitors. The company claims similar advantage on standby power.
So where is the advantage coming from? The simple answer is that the SiliconBlue devices have been designed from a clean sheet of paper to exhibit low power in moderate-speed applications. It’s not a matter of a single silver bullet, but rather a consistent approach to a goal.
This drive starts at the process level, according to Shankar. SiliconBlue uses vanilla CMOS, allowing the company to benefit immediately from low operating voltage. The fact that the chips are designed for moderate performance—they only have to be faster than competing ultralow-power FPGAs, not faster than the latest 10W bleeding-edge parts—allows SiliconBlue to choose low operating voltage on low-leakage libraries at 65 nm and still meet performance goals. The company also made judicious choices in transistor sizing and doping to further reduce power.
Circuit design plays a role too, Shankar says. The company designed the all-important lookup tables with complementary logic rather than the faster n-channel circuitry. Designers used register macros rather than SRAM macros for memory on the chips, again reducing both static and dynamic power. And they provided power-down circuitry for both multiplexers and interconnect links that are not in use. "We had a lot of circuit flexibility because we had this inherent speed advantage compared to the older processes other low-power products use," Shankar observes.
All of these factors should give the devices a significant power advantage over other moderate-sized FPGAs using significantly larger geometries in order to accommodate flash or antifuse technology. But what about direct comparison to the latest 45-nm-node parts that will be coming from Altera and Xilinx? SiliconBlue points to one more significant difference that distinguishes its offerings from these parts: the SiliconBlue FPGAs require no external configuration memory.
Conventional SRAM-based FPGAs are of course volatile: they lose their configuration shortly after the power goes down, and must be reloaded from an external memory on power-up. This consumes time and energy—especially when dealing with the power-on inrush currents of the devices—and it seriously limits the degree to which the FPGAs can be power-gated during operation. It also requires additional board space. Some users have circumvented the latter problem with mutlidie packaging, stacking the configuration flash die on top of the FPGA at some additional cost.
In contrast, the SiliconBlue parts also configure themselves at power-up, but they have a configuration memory on the die, as a one-time-programmable ROM array. The chips are designed to use either external configuration memory or the internal ROM, based on a switch setting. Using the internal ROM, the FPGAs load a configuration without a lot of external electrical activity.
To implement the internal ROM without incurring the penalties of a non-standard process, SiliconBlue uses a logic-compatible, 1.5-transistor oxide-disruption ROM cell technology derived from work done at Kilopass. "Our technology started there, but split off from theirs as the companies went different directions," Shankar explains. The entire configuration memory for a SiliconBlue device occupies about 2.5% of the die area, according to Shankar. There is an on-chip 6.5V bias generator for programming the one-time-programmable cells, so in-circuit programming requires little external circuitry.
All these distinctions give SiliconBlue a shot at two markets in which FPGAs have been notably unsuccessful in the past, according to Shankar. The CEO notes that FPGAs are in fact already accepted in consumer electronics: for example, moderate-sized FPGAs have prospered as interconnect bridges and logic extenders in format converter boxes and high-definition TVs. But these are applications that are both tethered to a source of line power and relatively high-cost.
Handsets, in contrast, have been almost immune to the appeals of the FPGA. Both the cost and—primarily—the energy consumption over realistic use profiles have made the handset unfriendly to even small PLDs used as glue logic, and outright hostile to FPGAs large enough to implement significant hunks of system core logic.
Shankar believes the SiliconBlue combination of logic density up to about 8000 logic cells, the previously stated low dynamic and static power, and high-volume unit cost in the few-dollars range, augmented by the advantage of no external ROM, will break open this barrier. He sees the parts finding use in the more expensive smartphones, both as application accelerators to ease the load on the applications CPU and to reduce energy for compute-intensive tasks, and as companion chips to the central SOC to provide product line flexibility and bug fixes.
If there is an obvious weakness to this story it is applications support. SiliconBlue has just over 20 employees in the USA, another dozen in China, and some contract relationships with other design teams. That has not left a lot of resources for tool or intellectual-property development. Accordingly, the company uses a Magma Design Automation front end tool chain, including Magma's timing-driven placement, coupled to a proprietary SiliconBlue router.
The difficult part of the story comes in the IP area. SiliconBlue currently offers about 30 elements in its IP libraly. Denny Steele, director of marketing and applications, says that the library comprises three sections. The first section is more in the way of design examples: "how to do this in our parts," he describes it. The second section contains application-specific designs such as voltage translator blocks. The third section includes major functional blocks such as a graphics controller. So far, as SiliconBlue has explored applications with its initial prospects, the latter blocks are necessarily based on customer request.
With a strong foundry relationship, proven interest from handset designers, and a roadmap to TSMC 40 nm, the company has a solid technical foundation. Shankar says SiliconBlue is sampling parts from its first family now. What happens next may depend both on the small company's ability to execute on a good idea, and on the response of the well-entrenched rest of the FPGA community, where an attempt to open the handset market to FPGAs will not go unnoticed.
© 2008, Reed Business Information, a division of Reed Elsevier Inc. All Rights Reserved.
NE ASIA-Korea 블루투스SIG(www.bluetooth.com)는 곧 발표될 블루투스 로우 에너지(Bluetooth Low Energy) 기술 표준이 가전업계에서 요구되는 상호운용성을 지원하는 범용 리모컨 규격을 제공할 것이라고 밝혔다. 저렴한 비용의 초저전력 애플리케이션을 가능케 할 블루투스 로우 에너지기술은 현재 개발 중에 있으며 내년에 발표될 예정이다.
블루투스 로우 에너지 기술은 몇 시간이 아니라 수년간 배터리 수명이 유지돼야 하는 디바이스와 서로 다른 제조사의 제품간 상호운용성이 요구되는 시장을 위해 설계됐는데, 이런 규격 특성은 리모컨의 요구 사항에 완벽하게 부합한다.
블루투스 로우 에너지 기술의 개발에는 노키아, 노르딕 반도체, 애질런트 테크놀로지스, TI, CSR 및 브로드컴을 포함해 48개가 넘는 기업이 참여하고 있다.
현재 무선 리모컨을 위한 표준은 없다. 새로운 블루투스 표준은 저비용, 비지능형 주변기기로서의 리모컨 개발을 가능하게 할 것이다. 블루투스 로우 에너지 리모컨은 TV, DVD 플레이어, 셋톱박스, 또는 미디어 플레이어 중 어떤 것이든 새로 구입한 디바이스에서도 작동이 가능하며, 그것이 제어하는 디바이스와 항상 안전하고 고유한 연결을 유지한다.
블루투스 로우 에너지 기술은 향후 수억 개의 휴대폰에 탑재될 것으로 보인다. 2009년 하반기에 이 기술이 탑재된 휴대폰이 출시되면 이는 곧 엄청난 양의 리모컨이 쏟아져 나오게 되는 것을 뜻한다.
단방향 제어만을 제공하는 현재의 리모컨 기술과 달리, 블루투스 로우 에너지 리모컨은 사용자에게 정보를 제공할 수 있다. 이로 인해 사용자는 TV 프로그램 직전에 관련 정보를 보는 대신, 셋톱박스 리모컨을 이용해 전자 프로그램 가이드를 보고 녹화형태를 미리 설정할 수 있다. 또한 외부의 인터넷 기반 서비스로 향하는 게이트웨이로 사용할 수도 있으므로, 안전한 주문을 위해 활용되거나 확장된 프로그램 정보를 보여줄 수도 있다.
| 김민기 |
| 한대수 |
| 산울림 |
내 컴퓨터로 들어온 내비게이션, 맵퍼스 아틀란 PC 라이트
- 제품 review 출처: 바이킹 (http://www.buyking.com/news/2008/05/news200805261422283)
- 제품 소개: http://www.atlan.co.kr/intro/pc_lite/pc_lite1.jsp
단, 사용기간이 "2009년 5월 1일"까지라는 것에 주의!!!
혹시 그때가면 또다른 버전이 지원될려나...?!