2006년 12월 28일 목요일

FPGA, EDA 위주의 다양한 bookmarks

Source: http://atrak.usc.edu/~changk/links.html

General CAD and VLSI Research Centers

Algorithm Research Centers

Mathematics and Optimization

FPGA related Research Centers

Computer Architecture

Low Power Research  Centers

Reconfigurable Computing


Software Defined Radio (SDR)

Embedded Programmable Logic Cores

Digital Signal Processing

On-Chip Cross-talk Modeling







Electronic Design Automation





Reconfigurable Computing

Computer Architecture


CAD Tools

Interesting Industry


Element CXI, Inc.


ElementCXI - Company Overview


Corporate – Company Overview
ElementCXI was founded in April 2004 as the next-generation semiconductor company. It’s founding is based on the realization that the delivery of real integrated circuit (IC) innovation has slowed – Silicon Valley being 40 years old – while the need for and the possibility of true innovation has accelerated in this ever-changing world. The ElementCXI team is combining the best of hardware and software to develop the next, wide-spread, general-purpose computing technologies and needed business models.

ElementCXI has development facilities/offices in Silicon Valley (Milpitas, California); Nashua, New Hampshire; and Tokyo, Japan.

ElementCXI’s Mission
Incorporated into the Company’s name is a constant reminder that customers must have the ability to Continuously Xccelerate (the) Innovation of their products.

ElementCXI’s Focus
Today, ODMs/OEMs everywhere are stifled with increasing electronic complexity, massive integration, slower and more expensive-to-develop applications, elongated time-to-market, decreasing return-on-investment, increased competition, and end-products that are increasingly likely to fail. Meanwhile, the Internet’s instantaneous flood of information and communication allows customers and competitors to immediately spread the word, stopping product sales worldwide if a usage problem occurs. The design effort, manufacture, and deployment of a new product are up against an inversely high-proportional set of risks. ElementCXI is focused on creating a highly advanced, next-generation technology that corrects these complex problems, enabling ODMs/OEMs to quickly and easily develop the best possible solution for their products.

The Need for a New Processing Solution
Despite enormous gains in raw computational power over the last two decades, it becomes increasingly clearer that a new IC approach is necessary to address the requirements of the 21st century. Whether or not the semiconductor industry continues doubling the number of transistors on a chip every 18 months, there continues to be no intelligent means to harness and use today’s raw computing power, and, we are continually defeated by the creation of larger, more complex systems.

Everyone knows the excitement of a new PC wears off quickly as its hard drive fills with complex and unreliable software code –the processor bogs down churning through unknown routines and the Internet allows infiltration of unwanted viruses. The raw computing power that so seductively invited us to build systems of unprecedented size and complexity has lead to products that are difficult to design, debug, monitor, and test. These systems regularly fail in practice, are increasingly vulnerable to unwanted intrusions, and are harder for the end-user to understand and use. These same issues occur in the embedded product space and the OEM is assigned the responsibility of filtering these issues from the end-user.

It’s also becoming apparent that growing system complexity may actually be reversing the information revolution. The cost of programming, building, and maintaining ever-more-complex systems has grown out of control. Finished products have shorter life cycles and decreasing return on investment (ROI), and users are constantly required to increase their technical expertise. The results are systems that grow more rigid, fragile, and unreliable, while end-users and ODMs/OEMs pay more to become more frustrated.

The design challenges that require complex SoCs with millions of lines of code, months to years of design time, and several IC re-spins must now meet market pressures that can no longer afford these costly and lengthy design cycles. A radical change in technology must take place in order to achieve a quantum leap in capability, productivity, and ease-of-use.

The current ICs and architectures that form the basis for Moore’s Law are predicated on the historical requirements of the 3Ps - performance, power consumption, and price. Until recently, it has been possible to largely ignore the dimension of the 3Rs – Robustness (resists a failure), Resilience (recovers despite a hard or soft failure), and true Reliability (continuous operation). As systems become more complex and IC fabrication geometries continue to decline, the 3Rs can no longer be ignored. The 3Rs provide the underpinning for products that are much faster and easier to design and use, have drastically reduced complexity, and that possess a quantum leap in system flexibility, upgradeability, security, and reduced software code – all while maintaining the original 3P requirements.

The attributes of the 3Rs also enable OEMs to Continuously Xccelerate (the) Innovation of their end products while quickly and easily meeting ever changing market demands. Rather than being behind the customers’ demands for new functionality and features, OEMs can supply products that exceed their customers’ desires – whether it’s a single customer or millions of customers.

Market Opportunity
ElementCXI is designing a general purpose processing platform suitable for any processing application. Element CXI’s initial focus is on three market opportunities:

  • Automotive electronics (telematics, communications, engine controllers)
  • Consumer wireless communications (handsets and PDAs)
  • Converging markets of digital imaging and 3D graphics (cameras, video, and analysis).

ElementCXI can then expand into markets as diverse as the following:

  • Consumer electronics (HDTV, digital TV, video compression, broadcast media)
  • Office imaging (digital imaging, digital printing)
  • General telecommunications (telecom infrastructure)
  • Wireless communications (base stations, satellite receivers)
  • Networking (data compression, encryption/decryption)
  • Multi-media (conferencing, video/image scaling)
  • Medical electronics (CAT scan, ultrasound)
  • Instrumentation and industrial test and measurement (robotic vision)
  • Military and security (security, scanning, biometrics)

ElementCXI - Management

Management Team
For over 20 years, the founding team and initial employees have been involved in key developments of integrated circuit (IC) fabrication processes, memory design, logic design, electronic design automation (EDA), reconfigurable computing, and IC manufacturing. They have invented and commercialized new fabrication processes, IC architectures, design tools, system OSs, RTOS kernels, and software control of real-time dynamic logic. The team has over 150 years of combined experience in high technology engineering and management, including the design, development, commercialization, marketing, sales, and product introductions of advanced electronic products and services.

Jaime Cummins
Chief Executive Officer and Founder
Jaime Cummins is the CEO and Founder of Element CXI. Mr. Cummins has over twenty years experience leading divisions and groups in the development of emerging wireless and wire-line communication systems, networking products, innovative software, and silicon technology. He most recently was a Co-Founder and former President and Chief Executive Officer (CEO) of QuickSilver Technology. At Xilinx, he was the Senior Director and General Manager of the Reconfigurable Logic Group that developed the XC6200, the first commercial RPU. Prior to Xilinx, Mr. Cummins was the Executive Director of Technology for Pacific Bell Video Services (PBVS) where he led the development and the first commercial deployments of broadband consumer services over a unified voice, data, and video network. At, Apple Computer, Mr. Cummins was Director of Macintosh System Software and was responsible for the development of the Macintosh System 7.5. He also was senior manager in the Macintosh Hardware Division, and Apple Integrated Systems Group. Mr. Cummins was a California State Scholar and holds a B.A. from the University of California at Santa Barbara. He attended the graduate school of Computer Science and Engineering at California State University at Sacramento.

John Watson
Vice President and Founder
John Watson is the Vice Presdient and Founder of Element CXI. Mr. Watson has more than twenty years marketing, sales, and senior management experience at Intel, Fairchild, National Semiconductor, Data I/O, and Xilinx, as well as a strong engineering background that dates back to the formative days of Intel. He was most recently a Co-Founder and Vice President Marketing of QuickSilver Technology, the pioneering company of adaptive computing technology. Mr. Watson’s focus is on innovating and delivering industry-first, leading-edge products throughout United States, Europe, and Southeast Asia/Japan geographies. While at QuickSilver, Mr. Watson was a co-developer of the Adaptive Computing Machine (ACM), a new class of high performance/low power IC, and developed the market for this technology. At Xilinx, he was responsible for developing and establishing the market category of reconfigurable computing, using Xilinx FPGA-based technologies. During is career at Data I/O, he played a key role in developing the market for and acceptance of FPGA technologies in 1989, as well as developing the world’s first FPGA emulator and software design tools Mr. Watson has been a co-founder of several industry tradeshows, magazines, and trade associations, promoting the advancement of IC technologies. He holds a BSEE from the University of Portland.

Robert (Bob) Barker
Director of Business Development
Robert Barker heads Business Development at Element CXI. Mr. Barker has over 20 years experience as a senior-level manager in the semiconductor, software and distribution industry. He held the position of Vice President of Marketing at Exemplar Logic, where he was responsible for the successful repositioning of the company from an OEM niche technology supplier to a mainstream FPGA synthesis end-user supplier. At Exemplar Logic, he introduced the highly successful Leonardo series of synthesis tools to the market, which contributed year-to-year revenue growth rates of 70 to 100 percent over a four-year period of time. Market valuation of Exemplar increased from $25M to $120M in two years. Prior to this, Mr. Barker was the Director of Marketing for the PLD Products Business Unit for Xilinx. At Plus Logic, an FPGA start-up, Mr. Barker participated in the initial funding of the company as a member of the management team that raised $5M in initial capital. He went on to found Plus Logic’s European subsidiary in Munich, Germany. Early in his career, Mr. Barker held marketing and sales positions at Hamilton/Avnet, Signetics, Intersil, and Mesa Engineering. He holds a BSEE from California Polytechnic State University.

Chris Phillips
VP of Engineering
Mr. Phillips has an extensive 20 year expertise in systems applications, micro-architectures, logic design, silicon level circuit design, algorithm invention, high level/assembly language programming, and code scripts. He has brought to market 20 fully-functional-at-first-silicon device tape outs and has 23 patents in the design of microcontrollers, microprocessors, FPGAs, ASICs, reconfigurable computing systems and CAD EDA tools. Previous to ElementCXI, he co-founded Tiger Semiconductor, Leopard Logic, and Chameleon Systems . At Summitt Design, Mr Phillips was Director of High Level Synthesis and at DaSys Inc. he pioneering behavioral synthesis. At Crosspoint Solutions, Mr. Phillips served as Director of Advanced Architecture for the CrossFire FPGA family and at National Semiconductor he designed and delivered the control and decode logic for a fully compatible, clean room 486 processor producing functional silicon and 8 patents in 15 months. Earlier, he was the designer responsible for the COP444C micro-controller which then averaged $80M/year revenue for 17 years so that, on average, every person in the US owns at least three of these devices. Chris Phillips graduated with a Bachelor of Science degree in Electrical Engineering from Cornell University in Ithaca , New York ; McMullen Scholar.

Dr. Sam Beal
Director of Applications
Sam has 26 years experience in engineering and marketing of semiconductor products, encompassing CMOS process and design, ASIC methodology and design services, FPGA applications and product planning, and system in package (SiP) development. As Senior Member of the Technical Staff, he developed Texas Instruments' initial standard cell methodology and later established and managed TI's first ASIC design center. He built and managed teams responsible for applications engineering, technical marketing, product marketing, and 3rd party IP at Hitachi , Actel and Alpine Microsystems. Sam has 6 patents granted, 4 pending, 25+ published articles and numerous conference presentations throughout the US , Europe and Japan. He holds a Ph.D in EE from SMU, Dallas Tx.

Dale Wong
Director of Software development
Prior to Element CXI, Dale Wong was a founder, V.P. of Technology for Leopard Logic, a
start-up company dedicated to the realization of data intensive algorithms in silicon. There he was responsible for global technology strategy and achievement of commercial quality results. Dale was also a founding member of Chameleon Systems from 1997-2000, where he was VP of Software development for ground-breaking development of the world’s first commercial reconfigurable communications platform. Mr. Wong received key seminal patents in the application of dynamic adaptive reconfigurability for algorithm acceleration. Dale has written and directed key platforms in both start-up and large corporate development environments at companies such as VLSI Technology, Crosspoint Solutions, and Cadence Design Automation in senior contributory roles. Mr. Wong has received 16 USPTO patents in area’s of advanced algorithm application and design.

© Copyright 2005-2006, Element CXI, Inc. All rights reserved.

2006년 12월 27일 수요일

Emailing: "라우팅 및 원격 액세스" "이름 확인" - Google 검색

The message is ready to be sent with the following file or link attachments:
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Adeurian D. Sapienneu :: 윈도우 구동 서비스와 포트번호

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2006년 12월 20일 수요일

갈수록 교묘해지는 e메일 스팸 - e메일 스팸도 ‘2.0시대’를 맞았다.

갈수록 교묘해지는 e메일 스팸

e메일 스팸도 ‘2.0시대’를 맞았다.

스팸메일이 여전히 기승을 부리고 있는 가운데 날로 첨단화하는 안티 스팸 기술에 대응해 스팸 발송 기술도 진화를 거듭하고 있는 것으로 나타났다.

뉴욕타임스는 스팸메일 필터 업체 아이언포트 자료를 인용해 지난해 말 기점으로 스팸메일 건수가 다시 늘고, 발송 기법 또한 교묘해졌다고 소개했다. 특히 기존 스팸 필터를 무력화할 수 있는 첨단 기술로 무장한 스팸메일인 스팸 2.0이 잇따라 출현 중이라고 전했다.

스팸 2.0은 기존 필터 기술을 교묘하게 피할 수 있는 신종 스팸메일. 기존 스팸 차단 기술은 크게 메일 발송자를 분석해 추적하거나, 텍스트에 포함된 단어로 메일을 걸러내고 연결된 웹사이트 검색를 통해 스팸메일 여부를 파악하는 등 3가지 방법을 사용했다.

스팸2.0은 한 마디로 이를 피해 갈 수 있는 새로운 형태의 지능형 메일.

먼저 스패머는 ’봇넷(botnet)’으로 불리는 해킹 프로그램을 사용해 자신의 컴퓨터가 아닌 다른 컴퓨터에서 스팸메일을 발송하는 방법을 쓰고 있다. 또 특정 문구를 걸러 내는 메일 텍스트 분석을 피하기 위해 이미지 속에 광고 문안을 넣어 만든 ‘이미지 스팸’ 형태로 진화하는 상황이다.

아이언포트는 이미지 스팸 발송량이 매년 크게 증가해 전체 스팸메일 중 최고 45%까지 차지하고 있다고 집계했다. 또 스팸메일 필터가 스팸메일 복사본을 찾아내 차단하지 못하도록 이미지를 조금씩 변경하는 스팸 기술까지 등장했다.

콕스커뮤니케이션스 전산 담당자인 프랭클린 왈릭은 “올해 들어서 기존 필터에 걸러지지 않는 스팸메일이 쏟아지고 있다”며 “내부에서 스팸메일 필터를 이제 사용하지 않고 있냐는 질문을 받을 정도”라고 말했다.

특히 신종 스팸메일은 미국 뿐 아니라 유럽·아시아·아프리카 등에서 무차별적으로 발송되고 있으며 지난 6개월 동안 크게 증가해 e메일 10통 가운데 9통이 스팸메일일 정도로 극성을 부리고 있다.

강병준 기자

[전자신문 2006-12-08]
 출처 : 전자신문 [2006/12/08 ]

2006년 12월 12일 화요일

사이커넥트, 디지털 전력선 트랜시버 칩 개발

사이커넥트, 디지털 전력선 트랜시버 칩 개발
게재: 2006년 12월 01일

사이커넥트의 디지털 전력선 트랜시버 칩 PLT050

사이커넥트(SiConnect)가 자사 최초의 디지털 전력선 트랜시버 칩 PLT050을 개발했다고 밝혔다.

ADSL 속도를 지원할 수 있도록 설계된 PLT050은 헤드라인 대역폭이 85Mbps 정도인 경쟁 솔루션의 성능과 맞먹는 14Mbps의 페이로드 쓰루풋(실제)을 달성한다.

양방향 아날로그/디지털 인터페이스 IC(AD9865), 단순한 커플러 회로, 산업 표준 PHY(이더넷, USB 또는 직렬) 및 시스템 펌웨어 및 구성 업로드를 위한 512kbit EEPROM 와 함께 사용되는 이 칩은 최소한의 외부 부품만으로도 완벽한 전력선 트랜시버 솔루션을 구현할 수 있다.

대체 전력선 트랜시버 솔루션과는 달리 POEM 기술 기반의 PLT050은 SMA/CR(Synchronous Multiple Access / Contention Resolution) 프로토콜과 16 서비스 레벨의 QoS 관리 기술을 이용해 오디오, 비디오, VoIP 및 IP 데이터 스트림간의 공정하고 우선적인 분배를 보장한다.

중요한 것은 PLT050을 이용하면, FCC Part 15, CISPR 22와 이의 유럽 지침인 EN55022(유럽에서 판매되는 가전에 요구되는 필수지침)를 포함해 글로벌 EMC 지침을 준수하는 제품을 만들 수 있다는 것이다.


자일링스, 마이크로블레이즈 개발 킷 출시

자일링스, 마이크로블레이즈 개발 킷 출시
게재: 2006년 11월 28일

마이크로블레이즈 개발 킷 ‘스파르탄-3E 1600E 에디션’

자일링스가 마이크로블레이즈(MicroBlaze) 개발 킷 ‘스파르탄-3E(Spartan-3E) 1600E 에디션’을 발표했다. 스파르탄-3E 1600E 에디션은 개발 과정을 시작하는데 필요한 하드웨어, 디자인 툴, 지적 재산권(IP), 레퍼런스 디자인을 모두 포함하는 통합 플랫폼을 제공한다.

통합 마이크로블레이즈 임베디드 개발 킷과 저렴한 스파르탄-3E플랫폼을 기반으로 하드웨어 및 소프트웨어 개발을 신속하게 실행할 수 있으며, 그 결과 저렴한 임베디드 솔루션의 개발을 가속화할 수 있다고 자일링스는 밝혔다.

마이크로블레이즈 개발 킷 '스파르탄-3E 1600E 에디션'은 자일링스 스파르탄-3E 시리즈 플랫폼 FPGA상에서 변화하는 임베디드 디자인 조건에 맞게 플랫폼을 조정할 수 있는 유연한 32비트 마이크로블레이즈 소프트 프로세서를 포함하고 있다.

개발 킷에 포함된 스파르탄-3E SP3E1600E 개발 보드는 플랫폼 로직, DSP 코프로세싱, 임베디드 시스템 통합 성능을 지닌 스파르탄-3E XC3S1600E-4FG320C 디바이스로, 설계자들이 간편하고 저비용으로 임베디드 시스템 디자인을 프로토타입 및 평가할 수 있도록 부품, 메모리, 디스플레이, 커넥터, 인터페이스의 다양한 옵션을 내장한다.

출처: http://www.eetkorea.com/ART_8800443316_839575_e94537f9200611.HTM

컨피규러블 섹션의 효과적인 설계

출처: http://www.eetkorea.com/ART_8800444031_839575_7bd74880_no.HTM

컨피규러블 섹션의 효과적인 설계
게재: 2006년 12월 01일

By Kiyosi Isihara
VP of Engineering
Viasic Inc.

점점 더 많은 수의 SoC 디자인들이 빠르고, 쉽고, 저렴하게 재프로그램되거나 리스핀될 수 있는 컨피규러블 섹션들을 포함시키고 있다. SoC의 구성성으로 디자이너들은 이제 비용을 걱정할 필요없이 마지막 스펙이 정해지기 전에 초기 버전의 제품을 내놓을 수 있기 때문에 관심이 집중되고 있는 제품을 시장에 첫 번째로 내놓을 수 있다. 컨피규러블 섹션들을 추가함으로써 업체들은 기능을 추가하거나 변경하고, 사소한 버그까지도 고칠 수 있으며, 서로 다른 시장을 위해 동일한 부품으로 서로 다른 버전들을 설계할 수 있다. 또, 고객의 특정 요구에 맞춘 기능들을 재빨리 추가해 새로운 비즈니스의 성공을 도울 수 있다.

이러한 컨피규러블 섹션들을 위한 하드웨어 패브릭들은 1)필드 프로그래머블, 2)메탈 프로그래머블, 2)스탠더드 메탈의 세 가지 범주에 들어간다.

필드 프로그래머블 패브릭들은 동일한 기본적 프로그래머블 빌딩 블록들을 이용하고, 구성성을 위해 메모리를 이용하며, 다재다능성을 제공한다. 그러나 필드 프로그래머블 패브릭들은 전력을 많이 먹으며, 다른 컨피규러블 패브릭들보다 칩 면적이 20배에서 50배 더 필요하다. 메탈 프로그래머블 패브릭들은 구식 게이트 어레이 기술의 가까운 사촌이며, 디자인을 프로그램하고 루팅하는데 3개에서 12개의 포토마스크가 필요하다. 스탠다드 메탈 패브릭은 사전 구성된 로직과 루팅을 가지고 있다. 그러나 구성성을 위해 큰 메모리를 갖는 대신 스탠다드 메탈 패브릭들은 프로그래밍을 위해 하나 이상의 마스크 레이어에 비아를 사용한다.

사용되는 패브릭에 상관없이 디자이너들은 SoC 내의 컨피규러블 섹션들을 디자인할 때 다음과 같은 지침에 주의해야 한다.

해야 할 일

·리스핀이 필요하게 될 가능성이 높고 재구성성의 이점을 가장 잘 살릴 수 있는 SoC 섹션에 대해 브레인스토밍한다. 비디오 코덱 알고리즘이 향후 바뀔 가능성이 있는가? 디자인의 특정 파트가 전통적으로 버그가 많았는가? IEEE 스펙은 새로 부상하는 기능을 위한 것인가? 이러한 모든 것들이 구성 가능한 블록의 후보가 될 것이다.

·컨피규러블 블록의 크기와 위치를 설정할 때 가능한 미래의 기능들을 명확하게 하라. 컨피규러블 영역을 미래에 사용할 수 없다면 컨피규러블 섹션을 가져야 할 이유가 없어진다. 필요한 컨피규러블 리소스들도 모든 목적에 충분해야 한다.

·효과적인 네트리스트 디자인을 위해 패브릭 리소스를 고려한다. 패브릭이 LUT에 기반을 둔 것이라면 여러 팬아웃을 가진 2입력 스테이지의 수를 최소화한다. 패브릭이 많은 미세한 특징들을 가지고 있다면 일반적으로 사용되는 2레벨의 인수화된 로직을 이용하라. 마찬가지로 패브릭이 컨피규러블 메모리를 가지고 있다면 레지스터 파일이나 다른 하드 코어화된 메모리 대신 이 메모리를 이용함으로써 훨씬 나은 전체 밀도를 얻을 수 있다.

·구성 가능한 패브릭의 바른 카테고리를 선택한다. 엔드유저가 엔드 디바이스를 재구성할 필요가 있다면 디자이너들은 필드 프로그래머블 패브릭을 선택해야 한다. 전력 소모, 열, 빠른 클럭 속도 또는 부품별 비용이 큰 문제가 된다면 디자이너들은 필드 프로그래머블 패브릭을 피해야 한다. 타임투마켓 또는 마스크 비용이 큰 문제라면 프로그래밍을 위해 단일 비아 레이어에 하나의 마스크 만을 필요로 하는 스탠더드 메탈 패브릭이 최상의 선택일 수 있다.

해선 안될 일

·컨피규러블 패브릭을 선택하는데 있어서 디자인 클로저에 들어가는 시간과 노력을 무시해서는 안 된다. 특히, 루팅이 장소에 구애받지 않고 자유로이 이루어지는 메탈 프로그래머블 패브릭에서 타이밍과 신호무결성의 디자인 클로저는 스탠더드 셀에서만큼 복잡할 수 있다.

·파운드리 공정의 라이프 스팬을 잊어서는 안 된다. 새로운 컨피규러블 SoC 플랫폼들은 수년 간 리스핀될 수 있어야 한다. 그리고 파운드리 공정이 수년 간 이용 가능해야 한다.

·컨피규러블 SoC와 관련된 비즈니스 문제들을 무시해선 안 된다. 엔지니어링 시간, 제조 시간, 마스크 비용이 모두 반영되었을 때 총 리스핀 비용은 얼마인가? 컨피규러블 패브릭이 로열티 비용을 수반한다면 이 또한 고려되어야 한다. 왜냐하면 이는 재정적인 재난을 초래하거나 아니면 프로젝트가 기대 이상의 물량으로 갈 때 경쟁력 없는 가격에 당신을 묶어둘 수도 있기 때문이다.

·제품 스펙이 완성되지 않았다는 핑계로 SoC 시작을 뒤로 미루어서는 안 된다. 컨피규러블 SoC는 새로운 제품을 시장에 빨리 내놓을 수 있게 해준다. 스펙이 일단 탄탄해지면 칩은 항상 리스핀될 수 있다. 마찬가지로, 컨피규러블 섹션에 늦게 변경 요청이 오더라도 땀 뺄 필요는 없다. 왜냐하면 모든 것을 다시 시작해야 하는 것은 아니기 때문이다.

·스탠더드 셀 생각에 사로잡혀서는 안 된다. 컨피규러블 로직을 갖는 이유는 여러 공급 제품들에 고유 IP를 이용하기 위해서이다. 마켓 윈도우가 더 까다롭고, 맞춤화와 새로운 기능들에 대한 요청이 더 많을수록 컨피규러블 SoC를 갖는 이점이 더 크다. 리스핀이 더 이상 문제가 되지 않는다는 점을 기억하자.

컨피규러블 블록이 융통성을 더해준다. 동일한 IP를 공유하는 서로 다른 SoC들은 신속하게 생산될 수 있다.

컨피규러블 블록이 융통성을 더해준다. 동일한 IP를 공유하는 서로 다른 SoC들은 신속하게 생산될 수 있다.

2006년 12월 5일 화요일

QUALCOMM Press Center - QUALCOMM to Acquire Airgo and Bluetooth Assets of RFMD

Hello All...

Qualcomm이 "RF Micro Devices, Inc. (http://www.rfmd.com/)"社의 Bluetooth 사업부문과 wireless LAN solution을 제공하는 private company인 "Airgo Networks Inc. (http://www.airgonetworks.com/)"社를 인수했습니다... 조만간 Qualcomm chipset 한종류로 모든 interconnectivity가 제공되는 황당(?)한 시절이 도래할지도 모른다는...

아래 press의 출처는 다음과 같습니다...


추가로 몇가지 press가 더 있는데 URL은 다음과 같습니다...

- Majority of RFMD's Bluetooth(R) Assets to Be Acquired by QUALCOMM,

- QUALCOMM Announces Availability of World’s First 802.11n Draft 2.0 Chipset,

Thanks... C.W. :)

QUALCOMM Incorporated / Press Release
5775 Morehouse Drive
San Diego, CA 92121-1714
(858) 587-1121

QUALCOMM to Acquire Airgo and Bluetooth Assets of RFMD

Move Enables Customers to More Quickly Deliver Industry-Leading Mobile Broadband Devices

SAN DIEGODecember 03, 2006 — QUALCOMM Incorporated (Nasdaq: QCOM), a leading developer and innovator of advanced wireless technologies and data solutions, today announced that it will be making acquisitions to complement its core wireless technology offerings. QUALCOMM will acquire for cash WLAN technology provider Airgo Networks Inc. and the majority of RF Micro Devices' (RFMD's) Bluetooth® assets. The acquisitions will enhance QUALCOMM's ability to deliver industry-leading, complete semiconductor solutions that will enable its device manufacturing partners to more quickly and easily offer a wide range of compelling wireless devices.

“QUALCOMM's business strategy has always been integration, enhancing performance and reducing time to market by offering complete solutions,” said Dr. Sanjay K. Jha, president of QUALCOMM CDMA Technologies. “With these two acquisitions, we will continue to extend our leadership in mobile broadband and will be offering our partners comprehensive chipsets with seamlessly integrated features.”

“As the attach rate for Bluetooth and WLAN features in mobile handsets is poised to grow past the critical tipping point, these acquisitions become very timely,” said Chris Ambrosio, director of wireless device strategies for Strategy Analytics. “With QUALCOMM now having the technologies of Airgo and RFMD's Bluetooth business in-house, manufacturers will have access to more integrated solutions - chipsets that deliver expanded, seamless connectivity with enhanced performance and space savings.”

Palo Alto, Calif.-based Airgo possesses intellectual property assets and resources in WLAN technology and has provided WLAN products to both manufacturers of access points and laptop computers. In addition to supporting Airgo's existing business, QUALCOMM will be integrating their 802.11a/b/g and 802.11n technology into select Mobile Station Modem™ (MSM™) chipsets. The Company will also use this technology for chipsets on the new Snapdragon™ platform, which is designed to offer ubiquitous mobile broadband connectivity.

“Airgo has an extensive history of delivering advanced wireless LAN solutions that have revolutionized our industry segment, and we are pleased to become part of the company we believe is the global leader in wireless technology and chipsets,” said Greg Raleigh, president & chief executive officer of Airgo Networks. “This acquisition enables integrated products with wireless LAN and wireless WAN capabilities to deliver a seamless-connectivity experience for users.”

Under the agreement with RFMD, QUALCOMM will acquire the majority of North Carolina-based RFMD's Bluetooth assets, specifically those based in San Diego. QUALCOMM will be integrating the Bluetooth Enhanced Data Rate (EDR) technology into MSM reference designs to offer its device manufacturing customers a more complete solution. RFMD's San Diego-based team currently designs technology for both the mobile handset and headset markets.

“RFMD hopes to become a broader development partner to QUALCOMM's entire product portfolio for complementary products such as power amplifiers and front-end modules,” said Bob Bruggeworth, president and chief executive officer of RFMD. “RFMD is pleased that QUALCOMM sees the value of our long-term roadmaps for front-end solutions. The sale of these assets is part of an ongoing relationship with QUALCOMM that we expect will continue to strengthen as we move forward to become the leading provider of high-performance radio systems and solutions to the wireless industry.”

QUALCOMM estimates the combined effect of these acquisitions on its pro forma earnings per share to be dilutive by approximately $0.04 in its fiscal year ending September 2007, and modestly accretive in FY08. The acquisitions are expected to close by the end of December 2006.

QUALCOMM Incorporated (www.qualcomm.com) is a leader in developing and delivering innovative digital wireless communications products and services based on CDMA and other advanced technologies. Headquartered in San Diego, Calif., QUALCOMM is included in the S&P 500 Index and is a 2006 FORTUNE 500® company traded on The Nasdaq Stock Market® under the ticker symbol QCOM.

Except for the historical information contained herein, this news release contains forward-looking statements that are subject to risks and uncertainties, including the ability to gain any necessary approvals for the proposed acquisitions, the successful completion of the acquisitions, the ability to achieve expected growth, savings and benefits of the acquisitions, the potential disruption in business or relationships with customers, vendors, partners and employees as a result of the proposed acquisitions, the Company's ability to successfully design and have manufactured significant quantities of CDMA components on a timely and profitable basis, the extent and speed to which CDMA is deployed, change in economic conditions of the various markets the Company serves, as well as the other risks detailed from time to time in the Company's SEC reports, including the report on Form 10-K for the year ended September 25, 2006.


QUALCOMM is a registered trademark of QUALCOMM Incorporated. Mobile Station Modem and MSM are trademarks of QUALCOMM Incorporated. The Bluetooth word mark and logos are owned by the Bluetooth SIG, Inc. All other trademarks are the property of their respective owners.

QUALCOMM Contacts:
Kira Lee, QUALCOMM CDMA Technologies
Phone: 1-858-845-7571
Email: qctpublicrelations@qualcomm.com

Emily Kilpatrick, Corporate Communications
Phone: 1-858-658-3143
Email: corpcomm@qualcomm.com

Garrett Ponder, Investor Relations
Phone: 1-858-658-4813
Email: ir@qualcomm.com


2006년 12월 4일 월요일





Gives the basic knowledge about modern design methods for digital systems.


There will be nine lectures given by the teachers.
Additional lectures will be dedicated to presentation of term papers (case studies) by the students.


P. Eles, K. Kuchcinski and Z. Peng "System Synthesis with VHDL" published by Kluwer Academic Publisher, December 1997.


Term paper and seminar presentation.


3 points.


Petru Eles, tel 28 13 96, e-mail petel@ida.liu.se.
Zebo Peng, tel 28 40 46, e-mail zebpe@ida.liu.se

Lecture Plan:

  • Thursday March 23, 10-12 in Elogen:
    Introduction and Course Overview. System Synthesis and High-Level Synthesis (Petru Eles).
    lecture notes
  • Thursday April 6, 10-12 in Elogen:
    VHDL - Basics and Simulation Mechanism (Petru Eles).
    lecture notes
  • Thursday April 13, 10-12 in Elogen:
    High-Level Synthesis (Zebo Peng).
    lecture notes
  • Thursday April 20, 10-12 in Elogen:
    Basics of Transformational Approach (Zebo Peng).
    lecture notes
  • Thursday April 27, 10-12 in Elogen:
    Optimization Heuristics for Synthesis (Zebo Peng).
  • Thursday May 11, 13-15 in Elogen:
    System-Level Synthesis and Hardware-Software Partitioning - I (Petru Eles).
  • Thursday May 18, 10-12 in Elogen:
    System-Level Synthesis and Hardware-Software Partitioning - II (Petru Eles).
  • Wednesday May 31, 10-12 in Eliten:
    Synthesis of Advanced Features (Petru Eles).
  • Thursday June 8, 10-12 in Elogen:
    High-Level Synthesis for Testability(Zebo Peng).
  • Thursday June 15, 10-?? in Elogen
    Presentation of Term Papers.

20-April-2000 21:22

Emailing: Papers on FPGA


  CAD Group Publications  Publications

keyword: FPGA
Found 30 entries [breakdown]
  1. Exploiting Circuit Emulation for Fast Hardness Evaluation
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 48, No. 6, December 2001, pp. 2210-2216

  2. A new functional fault model for FPGA Application-Oriented testing
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 372-380

  3. An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing:Theory and Applications, Vol. 18, No. 3, June 2002, pp. 261-271

  4. An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 602-607

  5. Analyzing SEU Effects in SRAM-based FPGAs
    M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 119-123

  6. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2088-2094

  7. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
    M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella,, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
    DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193

  8. On the evaluation of SEU sensitiveness in SRAM-based FPGAs
    P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 115-120

  9. A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
    F. Corno, J. Perez, M. Sonza Reorda, M. Violante
    SBCCI04: IEEE Symposium on Integrated Circuits and Systems Design, 2004, pp. 71-75

  10. Coupling Different Methodologies to Validate Obsolete Microprocessors
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    DFT'04: The 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

  11. Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    XIX Conference on Design of Circuits and Integrated Systems, Bordeaux, France, November 24-26, 2004

  12. On-line Analysis and Perturbation of CAN Networks
    M. Sonza Reorda, M. Violante
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004, pp. 424-432

  13. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella
    IEEE Transactions on Nuclear Science, Vol. 51, No. 6, December 2004, pp. 3354-3359

  14. On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs
    F. Kastensmidt, L. Sterpone, M. Sonza Reorda, L. Carro
    DATE2005: IEEE Design, Automation and Test in Europe, 2005, pp. 1290-1295

  15. Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
    M. Sonza Reorda, L. Sterpone, M. Violante
    ETS2005: IEEE European Test Symposium, 2005, pp. 136-141

  16. Efficient Estimation of SEU effects in SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 54-59

  17. RoRA: Reliability-oriented Place and Route for SRAM-based FPGAs
    L. Sterpone, M. Sonza Reorda, M. Violante
    PRIME05: IEEE Ph.D. Research In Micro-Electronics & Electronics, 2005, pp. 147-150

  18. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 5, October 2005, pp. 1545 - 1549

  19. A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 6, December 2005, pp. 2217 - 2223

  20. A design flow for protecting FPGA-based systems against single event upsets
    L. Sterpone, M. Violante
    DFT2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 436 - 444

  21. A new approach to compress the configuration information of programmable devices
    L. Sterpone, M. Violante, M. Martina, G. Masera, A. Molino, F. Vacca
    DATE2006: IEEE Design, Automation and Test in Europe, 2006, pp. 1 - 4

  22. A Fault Injection Environment for SoPC's Embedded Microprocessors
    M. Portela-Garcia, L. Sterpone, C. Lopez-Ongil, M. Sonza Reorda, M. Violante
    LATW2006, 7th IEEE Latin-American Test Workshop, pp. 68-73

  23. A new approach to cope with single event upsets in processor-based systems
    M. Schillaci, M. Sonza Reorda, M. Violante
    LATW2006, 7th IEEE Latin-American Test Workshop, pp. 145-150

  24. A New Hybrid Fault Detection Technique for Systems-on-a-Chip
    P. Bernardi, L. M. Veiras Bolzani, M. Rebaudengo, M. Sonza Reorda, F. L. Vargas, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 2, Feb. 2006, pp. 185-198

  25. A new reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 6, June 2006, pp. 732 - 744

  26. Fault Injection-based Reliability Evaluation of SoPCs
    M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena
    ETS2006: IEEE European Test Symposium, 2006, pp. 75 - 82

  27. An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    IEEE Transactions on Nuclear Science, Vol. 53, Issue 4, August 2006, pp. 2054 - 2059

  28. Hardening FPGA-based systems against SEUs: A new design methodology
    L. Sterpone, M. Violante
    Academy Publisher Journal of Computers, Vol. 1, No. 1, April 2006, pp. 22 - 30

  29. Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante, F. Lima Kastensmidt, L. Carro
    [Accepted for publication on] JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers

  30. Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro’s PowerPC 405
    P. Bernardi, L. Sterpone, M. Violante, M. Portela-Garcia
    [Accepted for publication on] IEEE Transactions on Nuclear Science, 2006, Vol. x, No. y, December 2006, pp. z - w

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