Wednesday, March 10, 2010
Tier Logic has gotten the occasional mention in this blog as a startup specializing in 3D interconnect, but after the splash made by players such as Tabula, NuPGA, and Abound, one could almost be tempted to ask what the company would do for an encore. But on the eve of Tier Logic’s official “architectural announcement” of March 10, Tier’s vice president of sales and marketing Paul Hollingworth clued me in on the company’s threefold path to profitability, which frankly makes a lot more tactical sense than what I’ve heard from other startups of late.
The company relies on relatively traditional configuration logic in a nine-layer-metal base, but adds TFT-based configuration SRAM in a third dimension, which can be replaced by the ninth layer of metal as a ROM configuration layer when committing a design to production. Tier Logic deliberately chose Toshiba as a process partner for its low-temperature amorphous silicon process, well-characterized in the display industry, as a more straightforward and economic alternative to polycrystalline silicon.
While nothing sounds radical from an architectural standpoint, that is part of the point of providing designers multiple paths to design production, which carries the fringe benefit of giving Tier Logic multiple paths to profitability. Tier Logic is working with a core of customers today to convert traditional designs to its all-CMOS TierASIC devices. Within the second quarter of this year, Tier Logic will convert some existing designs to the TierFPGA device using TFT SRAM as configuration – and some of those designs may later convert to TierASIC if volume warrants. (Typical NREs for the ASIC conversion step will be less than $50,000.) By year’s end, as designers become familiar with the Mobius design suite that Tier Logic provided to first customers in early 2010, the company will accept verified designs as first-pass TierFPGAs, converting to the metal-characterized TierASIC when and if those customers desire.
Hollingworth got to play the ASIC-conversion game when he headed up the HardCopy effort at Altera. He said he was a little concerned about the number of FPGA startups being launched just as a major recession began, but examined the Tier Logic business plan and decided it had the best chance of actually carving a slice of market share from existing FPGA market leaders.
When Tier Logic can capture a customer’s attention, Hollingworth feels confident the smaller size and lower power dissipation of a TierFPGA can win customers from the Big Two. The Mobius suite, which uses standard capture and simulation tools, the Mentor Precision Synthesis package, and unique P&R and timing analysis tools from Tier Logic, offers a common flow for FPGAs and ASICs. The problem, as always, is gaining the customer’s mindshare as a startup. But Tier Logic figures its hurdles at breaking into the FPGA mainstream are less daunting than many FPGA startups, and the company may be right about that.
© Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
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출처: http://www.edn.com/fpgagurus/blog/890000689/post/1850053185.html
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