액텔, 하드형 ARM 코어 통합한 플래시 기반 FPGA 선보여

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액텔, 하드형 ARM 코어 통합한 플래시 기반 FPGA 선보여

게재:2010년05월14일

Dylan McGrath
EE Times

Actel사가 임베디드 디자이너들의 폭 넓은 관심을 끌만한 중요한 발전이라고 밝힌 플래시 기반 FPGA(field programmable gate array) 제품군을 출시했다. 이 FPGA 패브릭은 하드형(hard) ARM Cortex-M3 프로세서로 구축된 완벽한 마이크로컨트롤러 서브시스템 및 프로그램 가능형 아날로그 블록과 통합되어 있다. SmartFusion 제품군의 첫번째 제품은 대량 생산 중으로 현재 이용 가능하다.

Actel사에 따르면, 디자이너들은 SmartFusion 디바이스를 통해 보드 레벨을 변경하지 않고도 하드웨어/소프트웨어 트레이드오프를 즉시 최적화시킬 수 있다고 한다. 프로세서와 필수 글루 로직을 한 디바이스에 제공함으로써 성능과 비용 및 풋프린트의 이점을 제공한다고 Actel사의 경영진들은 밝혔다.

“SmartFusion은 CPU 코어만이 아니라 완전한 마이크로컨트롤러 서브시스템을 갖추고 있다”고 Actel사의 세일즈 및 마케팅 VP인 Rich Kapusta 씨는 말했다. “최초로 성능에 대한 타협 없이 FPGA 및 마이크로컨트롤러를 일부 프로그램 가능형 아날로그와 통합했다.”

컨설팅 업체인 Silicon Insider사의 사장인 Jim Turley 씨에 따르면, 디자이너들은 약 10년 동안 프로세서들을 FPGA에 통합시키기 위해 노력해 왔지만 프로그램 가능형 패브릭과 프로세서 아키텍처가 조화되지 못하고 이 구성요소들 간의 통신이 느려짐으로써 그다지 큰 성공을 이루지 못했다고 한다. “Actel사는 SmartFusion을 통해 일반적인 ARM 프로세서와 FPGA 패브릭을 결합시켰을 뿐만 아니라 이 둘을 원활하게 통신할 수 있는 방식으로 통합시켰다”고 Turley 씨는 말했다.

SmartFusion은 2005년에 시장을 강타한 Actel사의 첫번째 혼성신호 FPGA인 Fusion에서 발전된 제품이다. Fusion 디바이스는 32비트 ARM Cortex-M1 등의 소프트 프로세서 코어를 통합할 수 있다.

Actel사의 마케팅 및 엔지니어링 수석 VP인 Fares Mubarak 씨는 Fusion이 시장에서 성공을 거두긴 했지만 Actel사는 타깃 어플리케이션의 폭을 보다 넓히고 싶어했다고 밝혔다. 이를 위해 Actel사는 프로세서를 강화하고 표준 주변기기에 대한 전체적인 보완 요소를 제공함으로써 프로세서 이외의 성능도 높여야만 했다.

“Actel사는 플래시 공정에 상당한 투자를 했기 때문에 이 새로운 제품군이 누구도 쉽게 복제할 수 없는 지속 가능하며 차별화된 디바이스라는 점에 대해 상당히 만족해 했다”고 Kapusta 씨는 말했다.

SmartFusion은 내장 플래시 메모리를 갖춘 CortexM3를 제공하는 한편, SRAM 기반 FPGA는 외장 플래시를 필요로 한다고 Kapusta 씨는 덧붙였다. 또한 그는 이러한 플래시 기술을 통해 SmartFusion에서 고전압 아날로그가 디지털 회로와 공존할 수 있는 것이라고 설명했다.

Actel사는 SmartFusion이 FPGA, 프로그램 가능형 아날로그 및 마이크로컨트롤러가 교차하는 광범위한 시장의 흥미를 끌 수 있을 것으로 생각하고 있다. SmartFusion은 산업, 군사, 의료, 통신, 컴퓨팅 및 스토리지 시장의 시스템 및 전력 관리, 모터 제어, 산업 자동화, 디스플레이와 같은 다양한 어플리케이션들을 타깃으로 하고 있다.

그러나 Actel사의 경영진들은 SmartFusion이 학습 곡선이 필요할 수도 있다면서, 특히 FPGA는 익숙하지만 마이크로컨트롤러에 대해서는 생소하다거나 그 반대의 상황인 디자이너들의 경우 그러할 것이라고 인정했다.

따라서 Actel사는 이 디바이스를 위한 설계 지원을 위해 Libero IDE(Integrated Design Environment)를 제공하며 GNU를 갖춘 무료 SoftConsole Eclipse 기반 IDE뿐만 아니라 Keil 및 IAR Systems사의 평가 소프트웨어 버전을 제공한다.

Actel사에 따르면, SmartFusion 디바이스에 통합된 마이크로컨트롤러 서브시스템은 ARM Cortex-M3 기반으로 100MHz 동작 속도를 가진다고 한다. 또한 최대 512킬로바이트의 플래시 메모리와 64킬로바이트의 SRAM 등이 포함되어 있다.

SmartFusion 디바이스는 Actel사의 플래시 기반 ProASIC3 FPGA 아키텍처로 제작되고 130나노 CMOS 공정에서 구현되며 6만~50만 개의 시스템 게이트와 350MHz의 성능으로 최대 204개의 입출력을 지원한다.

Actel사는 지난해 9월 이후부터 SmartFusion 디바이스를 샘플링해 왔으며 수십 곳의 고객사들과 협력을 진행해 왔다고 밝혔다. SmartFusion 제품군의 첫번째 제품인 A2F200은 대량 생산 중으로 현재 이용 가능하다. 또한 A2F500 디바이스들은 올해 2분기에 공급될 예정이며 A2F060 디바이스들은 올해 하반기에 공급될 전망이다.

고객 평가를 위한 샘플 개발 킷은 99달러에 제공되고 모든 기능을 갖춘 개발 킷은 999달러에 공급되며 두 개발 킷 모두 현재 바로 사용할 수 있다고 Actel사는 밝혔다.

본 기사는 http://www.eetkorea.com/ART_8800606711_480103_NP_dc456e9e.HTM에 있는 전자 엔지니어 기사에서 인쇄한 것입니다.

Digital camera differentiates itself by adding a second display

Performing a Tear Down on the Samsung TL225 digital camera revealed how they kept the BOM under control while expanding on the features.

By Richard Nass

Embedded.com (12/10/09, 09:47:00 AM EST)

It must be difficult for digital still camera vendors to differentiate their products from those of competitors, at least in the eyes of consumers. They can compete on resolution, battery life, image quality, etc. But those features are hard for the consumer to visualize, at least while in the store making a purchase. When you can come up with something that's truly different, then you have something you can really sink your marketing teeth into.

That's what the designers at Samsung have come up with—a digital still camera with a truly differentiating feature. The TL225, which happens to be the object of my current Tear Down, is built with a secondary display. It has the usual 3.5-in. display on the back. But the key is that it has a secondary display, measuring 1.5-in., on the front side of the camera.

The Samsung TL225 digital camera offers a differentiating feature—a secondary display on the front side of the camera.

If you're a 40-something like me, you may question why there's a display on the front of the camera. But show that camera to one of your kids like I did, and they know exactly what it's for—to take a picture of yourself or you and your buddies together.

The key for Samsung was to not raise the BOM much beyond what's required for a single-display camera. And they seem to have achieved that. Taking the camera apart showed that there are two key ICs on the board in addition to the memory.

Samsung was able to keep the BOM to a minimum by keeping the number of components to a minimum.

The Coach 10 device, from Zoran, drives the main display and also handles all the data conversion for the secondary display. In essence, the IC is connected to the image sensor on one side and the LCD on the other side. In between is the interface to the flash memory. The part corrects for image stabilization, lighting, and barrel effect, both in still mode and high-definition video mode.

Zoran claims to offer more than just the silicon. They provide many of the necessary algorithms, and even a reference platform that's pretty close to everything an OEM needs to go to market with a finished product. The Coach 10 also appears in Cisco's Flip UltraHD digital camcorder, which we took apart a few months ago.Note that Zoran has since released the next two devices in the Coach family, the 11 and 12. Those parts add features like face tracking, blur correction, noise reduction, and real-time lens distortion compensation.

The second part on the board is an Igloo AGL060 device from Actel, measuring 6 mm on a side. It's a flash-based FPGA that consumes very little power, operating down to 1.2 V. This particular part contains 60,000 gates and 96 user I/Os.

The Igloo FPGA is responsible for two key functions. One is to manage the interface between the Zoran part and the memory. And the second is to handle the interface to the secondary display. Hence, it's responsible for the LCD timing control and video downscaling.

The Igloo probably could have reduced some of the processing burden in the Zoran processor, had the Samsung designers chosen to do that. While that may have allowed for a slightly less powerful main processor, it would have required a lager die for the FPGA. That's an architectural decision the system engineer has to make. But the guess here is that they likely could have reduced both the bill-of-materials (BOM) and the power consumption slightly.

One of the nice features of the Igloo is that it can operate as either the master or the slave for power control. With a feature called Flash Freeze, the device goes into a very low power mode, around 10 μW. In this state, even though there's no logic toggling, I/Os can still be receiving data. But there's no power being consumed at the I/O or core level. Because the FPGA is flash-based, the value of the registers (or the memory itself) is not lost. Externally, there's no need to switch off the power, or gate or turn off the clock.

The software development for the camera was a designed mostly by Samsung, with drivers coming from Zoran and Actel. That makes the integration and validation a little tricky, because at the end of the day, or the end of the design in this case, all the pieces have to fit together, especially in terms of the timing and I/O assignments. Hence, there's a lot of finger crossing when you get to the validation stage. But in the case of the TL225, it's obvious that they got everything worked out, as the camera shipped on schedule.

On such a system, overall system validation could be difficult, in terms of developing pieces of code, making sure the timing and I/O assignments are accurate. You also have to make sure the footprint is right in terms of having everything fit properly on the board. I know that sounds obvious, but it should not be taken for granted.

Keeping the footprint as small as possible was key to the design.

The system's designers tell me that it worked right the first time, with just a little tweaking required on both the hardware and the software. This was likely because each subsystem was tested individually along the way. That increases the probability of things working correctly when they're all assembled together.

The design time for the TL225 was roughly five months from concept to completion. That's typical for a project like this one. While some of the pieces were new to this design, some IP was borrowed from previous designs, thereby fast-tracking the project somewhat.

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출처: http://www.embedded.com/underthehood/222001462

Emailing: 삼성, 듀얼 LCD카메라 8주만에 30만대 판매

삼성, 듀얼 LCD카메라 8주만에 30만대 판매

[ 2009-10-13 ]

삼성이 출시한 '듀얼 LCD카메라(ST550·500)'가 출시 8주 만에 30만대가 팔렸다. 세계 시장에서 1분에 4대 꼴로 팔린 셈이다. 　삼성디지털이미징(대표 박상진)은 지난 8월 출시한 듀얼 카메라 모델이 전 세계 300달러 이상 콤팩트 카메라 시장에서 9월 평균 판매량 15%를 차지했다고 밝혔다. 회사 측은 카메라 앞면에 LCD를 장착한 아이디어가 다양한 소비자 계층을 만족시킨 점을 성공 비결로 분석했다. 앞면 LCD 스크린은 '셀프 샷' 뿐 아니라 어린 아이 시선을 집중시키고 단체 사진을 찍을 때 카운트다운을 표시해 좋은 반응을 얻었다. 삼성 측은 경기 침체로 전체 카메라 시장이 10% 이상 줄고 저가 제품이 주로 판매되는 시장 상황에서 혁신 기능으로 프리미언 시장에서 점유율을 높였다는 데 의미를 부여했다. 이 회사 박상진 사장은 "소비자 입장에서 만든 제품은 소비자가 먼저 안다는 것을 보여 주는 좋은 사례"라고 말했다. 　 삼성 측은 1억 2000만대로 추정되는 올해 전세계 콘팩트 카메라 시장에서 300달러 이상 제품은 월평균 100만대 이상을 차지할 것이라고 낙관했다. 　 이수운기자 pero@etnews.co.kr   　 출처: http://www.etnews.co.kr/news/detail.html?id=200910120178

Copyrightⓒ 2000-2008 ELECTRONIC TIMES INTERNET CO., LTD. All Rights Reserved.

 

 

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Control issues: How FPGAs can address MCUs' general-purpose I/O scaling wall

September 09, 2009

By Mike Brogley, Actel Corp.

Microcontrollers, in many ways, are the indispensable engines of our world. With hundreds of billions of them in use, MCUs play a variety of different but equally important roles in almost every electronics application imaginable. Inexpensive, easy to use and well understood, MCUs are an integral part of a design engineer's toolkit—and she can choose from thousands of controllers and controller variations.

But controllers do run into limits. The general-purpose input and output (GPIO) ports available for a microcontroller are usually limited in number. Many applications require more ports than are available on the microcontroller. And because GPIOs are used for a number of functions like serving as a gateway to numerous peripherals and buses, managing LEDs and interrupt sources, oftentimes more is better.

FPGAs, however, can be deployed to overcome this barrier by adding four 8-bit ports to any 8-bit microcontroller. With the broad IP libraries available from FPGA vendors today, it's a relatively straightforward endeavor. Take the 8051s soft microcontroller core. It can be configured as an 8-bit microcontroller, without sacrificing power budget, cost or board real estate.

The 8051s: History, Compatibility
Core8051s is an ASM51-compatible microcontroller core that can run programs written for the 8051. It contains the main 8051 core logic but no peripheral logic. Core8051s has an APB bus interface that can be used like the SFR bus to easily expand the functionality of the core by connecting it to existing APB IP peripherals. This allows users to configure the core with the peripheral functions, such as I/O ports that they need for their application.

It also features a high-performance 8-bit microcontroller, one clock per instruction and can be used with existing 8051 tools and code, among other things.

Configuration
The direction of each port can be configured as input or output on the fly . The microcontroller bus is compatible with CoreAPB3 (AMBA bus), and is tested and verified with an Actel ProASIC 3 device.

This design block can be used as a memory-mapped device of the 8051s embedded processor. The base address of this core is created during the processor configuration with Actel's SmartDesign tool. An active high chip select enables the block and several registers within the core are assigned offset addresses.

The design has four ports: PORT_A, PORT_B, PORT_C, and PORT_D. Each of these ports can be configured as either an input or output 8-bit port. For writing or reading data from any port, the direction (input or output) bit of the direction control register must be configured.


Click on image to enlarge.

To perform a write operation to any of these ports, first set the direction as output for the port, address the corresponding port and then write the data (data are written to the corresponding port output register.) When the WR signal is asserted, the output registers of that particular port are enabled. The content of the WRITE_DATA bus will be written to the output data register of the selected port on the rising edge of clock. The content of WRITE_DATA will remain at the port until the port content is overwritten.

For reading data from any port, set the direction of that port as input and load the address bus with the address of that port. Data will be transferred when RD is asserted for the READ_DATA bus and the controller will read the data.

Software and Test
The application software is written in C language. The program must be initially downloaded to the program memory of the 8051s. The offset address corresponding to the various registers is hardcoded.

When a write cycle has to be performed, the direction control bit is initially set, followed by a write to that port. For a read cycle, the corresponding direction control bit is set and a read is performed from that port.

Actel's SoftConsole v2.1 is used for the software development and the FS2' ISA-Actel51 console is used for executing the program.

The on-board switches are connected to one of the input ports (PORT_D) and the nLEDs on the board are connected to one of the output ports (PORT_C). The software program continuously reads from the input port and sends data to the output port. Whenever the switch positions are changed, the LED indications also change correspondingly.

This design can be used in microcontroller-based setups where the number of ports needed exceeds the number of ports available on a microcontroller integrated circuit. This design requires minimal FPGA resources and can be accommodated by most of Actel's IGLOO' and ProASIC3 FPGAs. Even though the design mentioned in this example is for four 8-bit ports, the code can be easily modified to add additional ports or change the width of the ports.

About the Author
Mike Brogley, IP and Solutions Product Marketing Manager, joined Actel in 2005, bringing 20 years of experience in the technology industry. Prior to joining the company, he spent more than 15 years at LSI Logic Corp., where he held a variety of technical, operational and management roles. Brogley holds a bachelor's degree in aeronautics from San Jose State University. He is a member of IEEE, AIAA and SAE and is a life member of AFCEA and USNI.

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출처: http://www.pldesignline.com/219700342